From 0421b7af56c10cca219081c0911a2a2ce4d5d0f0 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 27 Oct 2021 10:37:35 -0700
Subject: [PATCH] Changes for floating point sims

---
 .../regression/regression-wally.py            |   1 +
 wally-pipelined/regression/sim-wally          |   2 +-
 wally-pipelined/regression/sim-wally-batch    |   2 +-
 .../regression/wave-dos/peripheral-waves.do   |   2 +-
 wally-pipelined/testbench/testbench.sv        |   1 +
 wally-pipelined/testbench/tests.vh            | 302 +++++++++---------
 6 files changed, 158 insertions(+), 152 deletions(-)

diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index ec06956b3..79532c5c8 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -48,6 +48,7 @@ for test in tests64:
         cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
+#tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
 for test in tests32:
   tc = TestCase(
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index 9985a0086..1479d0079 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32m"
+vsim -do "do wally-pipelined.do rv32g arch32f"
 
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index 06a66a106..4b627b768 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64g arch64m
+do wally-pipelined-batch.do rv32g arch32f
 !
diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do
index 6eec4995d..f5382c3bc 100644
--- a/wally-pipelined/regression/wave-dos/peripheral-waves.do
+++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do
@@ -53,7 +53,7 @@ add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
 add wave -divider
 add wave -hex /testbench/PCW
 #add wave -hex /testbench/InstrW
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
+#add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
 #add wave /testbench/InstrWName
 add wave -hex /testbench/dut/hart/ReadDataW
 add wave -hex /testbench/dut/hart/ieu/dp/ResultW
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index d2c83a4c7..e7f7e1f5d 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -101,6 +101,7 @@ logic [3:0] dummy;
         "arch32priv":                     tests = arch32priv;
         "arch32c":      if (`C_SUPPORTED) tests = arch32c;
         "arch32m":      if (`M_SUPPORTED) tests = arch32m;
+        "arch32f":      if (`F_SUPPORTED) tests = arch32f;
         "imperas32i":                     tests = imperas32i;
         "imperas32p":                     tests = imperas32p;
         "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index 5a8878f36..fbe0d916c 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -668,158 +668,162 @@ string imperas32f[] = '{
     "rv32i_m/M/remu-01", "5010"
    };
 
-/*
   string arch32f[] = '{
     `RISCVARCHTEST,
-    "rv32i_m/M/div-01", "5010",
-    "fadd_b1-01", "",
-    "fadd_b10-01", "",
-    "fadd_b11-01", "",
-    "fadd_b12-01", "",
-    "fadd_b13-01", "",
-    "fadd_b2-01", "",
-    "fadd_b3-01", "",
-    "fadd_b4-01", "",
-    "fadd_b5-01", "",
-    "fadd_b7-01", "",
-    "fadd_b8-01", "",
-    "fclass_b1-01", "",
-    "fcvt.s.w_b25-01", "",
-    "fcvt.s.w_b26-01", "",
-    "fcvt.s.wu_b25-01", "",
-    "fcvt.s.wu_b26-01", "",
-    "fcvt.w.s_b1-01", "",
-    "fcvt.w.s_b22-01", "",
-    "fcvt.w.s_b23-01", "",
-    "fcvt.w.s_b24-01", "",
-    "fcvt.w.s_b27-01", "",
-    "fcvt.w.s_b28-01", "",
-    "fcvt.w.s_b29-01", "",
-    "fcvt.wu.s_b1-01", "",
-    "fcvt.wu.s_b22-01", "",
-    "fcvt.wu.s_b23-01", "",
-    "fcvt.wu.s_b24-01", "",
-    "fcvt.wu.s_b27-01", "",
-    "fcvt.wu.s_b28-01", "",
-    "fcvt.wu.s_b29-01", "",
-    "fdiv_b1-01", "",
-    "fdiv_b2-01", "",
-    "fdiv_b20-01", "",
-    "fdiv_b21-01", "",
-    "fdiv_b3-01", "",
-    "fdiv_b4-01", "",
-    "fdiv_b5-01", "",
-    "fdiv_b6-01", "",
-    "fdiv_b7-01", "",
-    "fdiv_b8-01", "",
-    "fdiv_b9-01", "",
-    "feq_b1-01", "",
-    "feq_b19-01", "",
-    "fle_b1-01", "",
-    "fle_b19-01", "",
-    "flt_b1-01", "",
-    "flt_b19-01", "",
-    "flw-align-01", "",
-    "fmadd_b1-01", "",
-    "fmadd_b14-01", "",
-    "fmadd_b15-01", "",
-    "fmadd_b16-01", "",
-    "fmadd_b17-01", "",
-    "fmadd_b18-01", "",
-    "fmadd_b2-01", "",
-    "fmadd_b3-01", "",
-    "fmadd_b4-01", "",
-    "fmadd_b5-01", "",
-    "fmadd_b6-01", "",
-    "fmadd_b7-01", "",
-    "fmadd_b8-01", "",
-    "fmax_b1-01", "",
-    "fmax_b19-01", "",
-    "fmin_b1-01", "",
-    "fmin_b19-01", "",
-    "fmsub_b1-01", "",
-    "fmsub_b14-01", "",
-    "fmsub_b15-01", "",
-    "fmsub_b16-01", "",
-    "fmsub_b17-01", "",
-    "fmsub_b18-01", "",
-    "fmsub_b2-01", "",
-    "fmsub_b3-01", "",
-    "fmsub_b4-01", "",
-    "fmsub_b5-01", "",
-    "fmsub_b6-01", "",
-    "fmsub_b7-01", "",
-    "fmsub_b8-01", "",
-    "fmul_b1-01", "",
-    "fmul_b2-01", "",
-    "fmul_b3-01", "",
-    "fmul_b4-01", "",
-    "fmul_b5-01", "",
-    "fmul_b6-01", "",
-    "fmul_b7-01", "",
-    "fmul_b8-01", "",
-    "fmul_b9-01", "",
-    "fmv.w.x_b25-01", "",
-    "fmv.w.x_b26-01", "",
-    "fmv.x.w_b1-01", "",
-    "fmv.x.w_b22-01", "",
-    "fmv.x.w_b23-01", "",
-    "fmv.x.w_b24-01", "",
-    "fmv.x.w_b27-01", "",
-    "fmv.x.w_b28-01", "",
-    "fmv.x.w_b29-01", "",
-    "fnmadd_b1-01", "",
-    "fnmadd_b14-01", "",
-    "fnmadd_b15-01", "",
-    "fnmadd_b16-01", "",
-    "fnmadd_b17-01", "",
-    "fnmadd_b18-01", "",
-    "fnmadd_b2-01", "",
-    "fnmadd_b3-01", "",
-    "fnmadd_b4-01", "",
-    "fnmadd_b5-01", "",
-    "fnmadd_b6-01", "",
-    "fnmadd_b7-01", "",
-    "fnmadd_b8-01", "",
-    "fnmsub_b1-01", "",
-    "fnmsub_b14-01", "",
-    "fnmsub_b15-01", "",
-    "fnmsub_b16-01", "",
-    "fnmsub_b17-01", "",
-    "fnmsub_b18-01", "",
-    "fnmsub_b2-01", "",
-    "fnmsub_b3-01", "",
-    "fnmsub_b4-01", "",
-    "fnmsub_b5-01", "",
-    "fnmsub_b6-01", "",
-    "fnmsub_b7-01", "",
-    "fnmsub_b8-01", "",
-    "fsgnj_b1-01", "",
-    "fsgnjn_b1-01", "",
-    "fsgnjx_b1-01", "",
-    "fsqrt_b1-01", "",
-    "fsqrt_b2-01", "",
-    "fsqrt_b20-01", "",
-    "fsqrt_b3-01", "",
-    "fsqrt_b4-01", "",
-    "fsqrt_b5-01", "",
-    "fsqrt_b7-01", "",
-    "fsqrt_b8-01", "",
-    "fsqrt_b9-01", "",
-    "fsub_b1-01", "",
-    "fsub_b10-01", "",
-    "fsub_b11-01", "",
-    "fsub_b12-01", "",
-    "fsub_b13-01", "",
-    "fsub_b2-01", "",
-    "fsub_b3-01", "",
-    "fsub_b4-01", "",
-    "fsub_b5-01", "",
-    "fsub_b7-01", "",
-    "fsub_b8-01", "",
-    "fsw-align-01, ""
+    // tests repeated up here for basic sanity
+    //"rv32i_m/F/flw-align-01", "2010", // passes
+    //"rv32i_m/F/fmv.w.x_b25-01", "2090", // passes
+    "rv32i_m/F/fmadd_b14-01", "23d0", // fails test 1
+    "rv32i_m/F/fcvt.s.w_b25-01", "20a0", // fails test 3
+    // main tests
+    "rv32i_m/F/fadd_b1-01", "7220",
+    "rv32i_m/F/fadd_b10-01", "2270", 
+    "rv32i_m/F/fadd_b11-01", "3fb40",
+    "rv32i_m/F/fadd_b12-01", "21b0",
+    "rv32i_m/F/fadd_b13-01", "3660",
+    "rv32i_m/F/fadd_b2-01", "38b0",
+    "rv32i_m/F/fadd_b3-01", "b320",
+    "rv32i_m/F/fadd_b4-01", "3480",
+    "rv32i_m/F/fadd_b5-01", "3700",
+    "rv32i_m/F/fadd_b7-01", "3520",
+    "rv32i_m/F/fadd_b8-01", "104a0",
+    "rv32i_m/F/fclass_b1-01", "2090",
+    "rv32i_m/F/fcvt.s.w_b25-01", "20a0",
+    "rv32i_m/F/fcvt.s.w_b26-01", "3290",
+    "rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
+    "rv32i_m/F/fcvt.s.wu_b26-01", "3290",
+    "rv32i_m/F/fcvt.w.s_b1-01", "2090",
+    "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
+    "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
+    "rv32i_m/F/fcvt.w.s_b24-01", "21b0",
+    "rv32i_m/F/fcvt.w.s_b27-01", "2090",
+    "rv32i_m/F/fcvt.w.s_b28-01", "2090",
+    "rv32i_m/F/fcvt.w.s_b29-01", "2150",
+    "rv32i_m/F/fcvt.wu.s_b1-01", "2090",
+    "rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
+    "rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
+    "rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
+    "rv32i_m/F/fcvt.wu.s_b27-01", "2090",
+    "rv32i_m/F/fcvt.wu.s_b28-01", "2090",
+    "rv32i_m/F/fcvt.wu.s_b29-01", "2150",
+    "rv32i_m/F/fdiv_b1-01", "7220",
+    "rv32i_m/F/fdiv_b2-01", "2350",
+    "rv32i_m/F/fdiv_b20-01", "38c0",
+    "rv32i_m/F/fdiv_b21-01", "7540",
+    "rv32i_m/F/fdiv_b3-01", "b320",
+    "rv32i_m/F/fdiv_b4-01", "3480",
+    "rv32i_m/F/fdiv_b5-01", "3700",
+    "rv32i_m/F/fdiv_b6-01", "3480",
+    "rv32i_m/F/fdiv_b7-01", "3520",
+    "rv32i_m/F/fdiv_b8-01", "104a0",
+    "rv32i_m/F/fdiv_b9-01", "d960",
+    "rv32i_m/F/feq_b1-01", "6220",
+    "rv32i_m/F/feq_b19-01", "a190",
+    "rv32i_m/F/fle_b1-01", "6220",
+    "rv32i_m/F/fle_b19-01", "a190",
+    "rv32i_m/F/flt_b1-01", "6220",
+    "rv32i_m/F/flt_b19-01", "8ee0",
+    "rv32i_m/F/flw-align-01", "2010",
+    "rv32i_m/F/fmadd_b1-01", "96860",
+    "rv32i_m/F/fmadd_b14-01", "23d0",
+    "rv32i_m/F/fmadd_b15-01", "19bb30",
+    "rv32i_m/F/fmadd_b16-01", "39d0",
+    "rv32i_m/F/fmadd_b17-01", "39d0",
+    "rv32i_m/F/fmadd_b18-01", "4d10",
+    "rv32i_m/F/fmadd_b2-01", "4d60",
+    "rv32i_m/F/fmadd_b3-01", "d4f0",
+    "rv32i_m/F/fmadd_b4-01", "3700",
+    "rv32i_m/F/fmadd_b5-01", "3ac0",
+    "rv32i_m/F/fmadd_b6-01", "3700",
+    "rv32i_m/F/fmadd_b7-01", "d7f0",
+    "rv32i_m/F/fmadd_b8-01", "13f30",
+    "rv32i_m/F/fmax_b1-01", "7220",
+    "rv32i_m/F/fmax_b19-01", "9e00",
+    "rv32i_m/F/fmin_b1-01", "7220",
+    "rv32i_m/F/fmin_b19-01", "9f20",
+    "rv32i_m/F/fmsub_b1-01", "96860",
+    "rv32i_m/F/fmsub_b14-01", "23d0",
+    "rv32i_m/F/fmsub_b15-01", "19bb30",
+    "rv32i_m/F/fmsub_b16-01", "39d0",
+    "rv32i_m/F/fmsub_b17-01", "39d0",
+    "rv32i_m/F/fmsub_b18-01", "42d0",
+    "rv32i_m/F/fmsub_b2-01", "4d60",
+    "rv32i_m/F/fmsub_b3-01", "d4f0",
+    "rv32i_m/F/fmsub_b4-01", "3700",
+    "rv32i_m/F/fmsub_b5-01", "3ac0",
+    "rv32i_m/F/fmsub_b6-01", "3700",
+    "rv32i_m/F/fmsub_b7-01", "37f0",
+    "rv32i_m/F/fmsub_b8-01", "13f30",
+    "rv32i_m/F/fmul_b1-01", "7220",
+    "rv32i_m/F/fmul_b2-01", "38c0",
+    "rv32i_m/F/fmul_b3-01", "b320",
+    "rv32i_m/F/fmul_b4-01", "3480",
+    "rv32i_m/F/fmul_b5-01", "3700",
+    "rv32i_m/F/fmul_b6-01", "3480",
+    "rv32i_m/F/fmul_b7-01", "3520",
+    "rv32i_m/F/fmul_b8-01", "104a0",
+    "rv32i_m/F/fmul_b9-01", "d960",
+    "rv32i_m/F/fmv.w.x_b25-01", "2090",
+    "rv32i_m/F/fmv.w.x_b26-01", "2090",
+    "rv32i_m/F/fmv.x.w_b1-01", "2090",
+    "rv32i_m/F/fmv.x.w_b22-01", "2090",
+    "rv32i_m/F/fmv.x.w_b23-01", "2090",
+    "rv32i_m/F/fmv.x.w_b24-01", "2090",
+    "rv32i_m/F/fmv.x.w_b27-01", "2090",
+    "rv32i_m/F/fmv.x.w_b28-01", "2090",
+    "rv32i_m/F/fmv.x.w_b29-01", "2090",
+    "rv32i_m/F/fnmadd_b1-01", "96870",
+    "rv32i_m/F/fnmadd_b14-01", "23d0",
+    "rv32i_m/F/fnmadd_b15-01", "19bb40",
+    "rv32i_m/F/fnmadd_b16-01", "39d0",
+    "rv32i_m/F/fnmadd_b17-01", "39d0",
+    "rv32i_m/F/fnmadd_b18-01", "4d10",
+    "rv32i_m/F/fnmadd_b2-01", "4d60",
+    "rv32i_m/F/fnmadd_b3-01", "d4f0",
+    "rv32i_m/F/fnmadd_b4-01", "3700",
+    "rv32i_m/F/fnmadd_b5-01", "3ac0",
+    "rv32i_m/F/fnmadd_b6-01", "3700",
+    "rv32i_m/F/fnmadd_b7-01", "37f0",
+    "rv32i_m/F/fnmadd_b8-01", "13f30",
+    "rv32i_m/F/fnmsub_b1-01", "96870",
+    "rv32i_m/F/fnmsub_b14-01", "23d0",
+    "rv32i_m/F/fnmsub_b15-01", "19bb30",
+    "rv32i_m/F/fnmsub_b16-01", "39d0",
+    "rv32i_m/F/fnmsub_b17-01", "39d0",
+    "rv32i_m/F/fnmsub_b18-01", "4d10",
+    "rv32i_m/F/fnmsub_b2-01", "4d60",
+    "rv32i_m/F/fnmsub_b3-01", "4df0",
+    "rv32i_m/F/fnmsub_b4-01", "3700",
+    "rv32i_m/F/fnmsub_b5-01", "3ac0",
+    "rv32i_m/F/fnmsub_b6-01", "3700",
+    "rv32i_m/F/fnmsub_b7-01", "37f0",
+    "rv32i_m/F/fnmsub_b8-01", "13f30",
+    "rv32i_m/F/fsgnj_b1-01", "7220",
+    "rv32i_m/F/fsgnjn_b1-01", "7220",
+    "rv32i_m/F/fsgnjx_b1-01", "7220",
+    "rv32i_m/F/fsqrt_b1-01", "2090",
+    "rv32i_m/F/fsqrt_b2-01", "2090",
+    "rv32i_m/F/fsqrt_b20-01", "2090",
+    "rv32i_m/F/fsqrt_b3-01", "2090",
+    "rv32i_m/F/fsqrt_b4-01", "2090",
+    "rv32i_m/F/fsqrt_b5-01", "2090",
+    "rv32i_m/F/fsqrt_b7-01", "2090",
+    "rv32i_m/F/fsqrt_b8-01", "2090",
+    "rv32i_m/F/fsqrt_b9-01", "3310",
+    "rv32i_m/F/fsub_b1-01", "7220",
+    "rv32i_m/F/fsub_b10-01", "2250",
+    "rv32i_m/F/fsub_b11-01", "3fb40",
+    "rv32i_m/F/fsub_b12-01", "21b0",
+    "rv32i_m/F/fsub_b13-01", "3660",
+    "rv32i_m/F/fsub_b2-01", "38b0",
+    "rv32i_m/F/fsub_b3-01", "b320",
+    "rv32i_m/F/fsub_b4-01", "3480",
+    "rv32i_m/F/fsub_b5-01", "3700",
+    "rv32i_m/F/fsub_b7-01", "3520",
+    "rv32i_m/F/fsub_b8-01", "104a0",
+    "rv32i_m/F/fsw-align-01", "2010"
 };
-*/
+
 
   string arch32c[] = '{
     `RISCVARCHTEST,