Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM

Browse Source
This commit is contained in:
David Harris 2022-08-26 21:05:20 -07:00
parent f0b4f69b65
commit 03e731b3ff
5 changed files with 9 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/config/rv64BP/wally-config.vh
View File

@ -91,11 +91,11 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 0 `define DTIM_SUPPORTED 0
`define DTIM_BASE 34'h80000000 `define DTIM_BASE 56'h80000000
`define DTIM_RANGE 34'h00001FFF `define DTIM_RANGE 56'h00001FFF
`define IROM_SUPPORTED 0 `define IROM_SUPPORTED 0
`define IROM_BASE 34'h80000000 `define IROM_BASE 56'h80000000
`define IROM_RANGE 34'h00001FFF `define IROM_RANGE 56'h00001FFF
`define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 56'h00001000 `define BOOTROM_BASE 56'h00001000
`define BOOTROM_RANGE 56'h00000FFF `define BOOTROM_RANGE 56'h00000FFF

7
pipelined/src/ifu/irom.sv
View File

@ -35,12 +35,9 @@ module irom(
output logic [31:0] ReadData output logic [31:0] ReadData
); );
localparam ADDR_WDITH = $clog2(`IROM_RANGE/8);
// localparam ADDR_WDITH = $clog2(`IROM_RAM_RANGE/8); // *** replace with tihs when defined
localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
localparam OFFSET = $clog2(`LLEN/8); localparam OFFSET = $clog2(`LLEN/8);
brom1p1r #(ADDR_WDITH, 32) brom1p1r #(ADDR_WDITH, 32) rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
endmodule endmodule

3
pipelined/src/lsu/dtim.sv
View File

@ -41,8 +41,7 @@ module dtim(
logic we; logic we;
// localparam ADDR_WDITH = $clog2(`TIM_RAM_RANGE/8); // *** replace with tihs when defined localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
localparam OFFSET = $clog2(`LLEN/8); localparam OFFSET = $clog2(`LLEN/8);
assign we = LSURWM[0] & ~TrapM; // have to ignore write if Trap. assign we = LSURWM[0] & ~TrapM; // have to ignore write if Trap.

1
pipelined/src/mmu/mmu.sv
View File

@ -135,7 +135,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers. // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit); assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);

2
pipelined/testbench/testbench.sv
View File

@ -439,7 +439,7 @@ module riscvassertions;
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
assert (`FLEN<=`XLEN | `DCACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported"); assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");