From 03cea6e29ba4728c4fda09c4e274074bef1eeb46 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 16:13:10 -0500 Subject: [PATCH] more misaligned read fixing I'm getting fairly concerned about this, I feel like this should only work if the memory ignores the lower 3 or 4 bits of the adr --- wally-pipelined/regression/wally-busybear.do | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index ab1cfac31..cd739993c 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -54,6 +54,7 @@ add wave -hex /testbench_busybear/MemRWM[0] add wave -hex /testbench_busybear/MemRWM[1] add wave -hex /testbench_busybear/ByteMaskM add wave -hex /testbench_busybear/WriteDataM +add wave -hex /testbench_busybear/ReadDataM add wave -hex /testbench_busybear/DataAdrM add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]