From 03aea055fac42bc72d3cdcc9f762ec1ea771b77b Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 24 May 2021 14:44:30 -0400 Subject: [PATCH] FMV.X.D imperas test passes --- wally-pipelined/src/fpu/fctrl.sv | 2 +- wally-pipelined/src/fpu/fpu.sv | 2 +- wally-pipelined/src/fpu/fpuhazard.sv | 2 +- wally-pipelined/src/ieu/datapath.sv | 5 +++-- wally-pipelined/src/ieu/forward.sv | 7 +++++-- wally-pipelined/src/ieu/ieu.sv | 2 ++ wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +- wally-pipelined/testbench/testbench-imperas.sv | 10 +++++----- 8 files changed, 19 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv index 7c9a8813a..f24368e17 100755 --- a/wally-pipelined/src/fpu/fctrl.sv +++ b/wally-pipelined/src/fpu/fctrl.sv @@ -206,7 +206,7 @@ module fctrl ( // fsw = ?010 // output Input2 // fsd = ?011 // output Input2 // fmv.x.w = ?100 - // fmv.d.w = ?101 + // fmv.x.d = ?101 // {?, is mv, is store, is double or fcvt.d.w} 3'b111 : begin OpCtrlD = {1'b0, OpD[6:5], Funct3D[0] | (OpD[6]&Funct7D[0])}; In2UsedD = OpD[5]; end default : begin OpCtrlD = 4'b0; IllegalFPUInstr1D = 1'b1; In2UsedD = 1'b0; end diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 9c096f4cc..3298e83ba 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -43,6 +43,7 @@ module fpu ( output logic [1:0] FMemRWM, output logic FStallD, output logic FWriteIntW, + output logic FWriteIntM, output logic [`XLEN-1:0] FWriteDataM, // Integer input being written into fpreg output logic DivSqrtDoneE, output logic IllegalFPUInstrD, @@ -336,7 +337,6 @@ module fpu ( logic [2:0] FrmM; logic FmtM; logic [3:0] OpCtrlM; - logic FWriteIntM; //instantiate M stage FMA signals here ***rename fma signals and resize for XLEN logic [63:0] FmaResultM; diff --git a/wally-pipelined/src/fpu/fpuhazard.sv b/wally-pipelined/src/fpu/fpuhazard.sv index 4fb4e65a7..ba7482511 100644 --- a/wally-pipelined/src/fpu/fpuhazard.sv +++ b/wally-pipelined/src/fpu/fpuhazard.sv @@ -48,7 +48,7 @@ module fpuhazard( Input3MuxD = 1'b0; FStallD = DivBusyM; if (~IllegalFPUInstrD) begin - +// if taking a value from int register if ((Adr1 == RdE) & (FRegWriteE | ((FResultSelE == 3'b110) & RegWriteD))) if (FResultSelE == 3'b110) Input1MuxD = 2'b11; // choose SrcAM else FStallD = 1'b1; // otherwise stall diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index b7c9acc33..13db65a37 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -44,6 +44,7 @@ module datapath ( output logic [`XLEN-1:0] SrcAE, SrcBE, // Memory stage signals input logic StallM, FlushM, + input logic [`XLEN-1:0] FWriteDataM, output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] WriteDataM, MemAdrM, // Writeback stage signals @@ -101,8 +102,8 @@ module datapath ( flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE); - mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE); + mux4 #(`XLEN) faemux(RD1E, WriteDataW, ALUResultM, FWriteDataM, ForwardAE, PreSrcAE); + mux4 #(`XLEN) fbemux(RD2E, WriteDataW, ALUResultM, FWriteDataM, ForwardBE, WriteDataE); mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2); mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE); diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv index d35745128..f00a6ecbc 100644 --- a/wally-pipelined/src/ieu/forward.sv +++ b/wally-pipelined/src/ieu/forward.sv @@ -31,6 +31,7 @@ module forward( input logic MemReadE, MulDivE, CSRReadE, input logic RegWriteM, RegWriteW, input logic DivDoneE, DivBusyE, + input logic FWriteIntM, FWriteIntW, // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, output logic LoadStallD, MulDivStallD, CSRRdStallD @@ -41,11 +42,13 @@ module forward( ForwardBE = 2'b00; if (Rs1E != 5'b0) if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10; - else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01; + else if ((Rs1E == RdW) & (RegWriteW|FWriteIntW)) ForwardAE = 2'b01; + else if ((Rs1E == RdM) & FWriteIntM) ForwardAE = 2'b11; if (Rs2E != 5'b0) if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10; - else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01; + else if ((Rs2E == RdW) & (RegWriteW|FWriteIntW)) ForwardBE = 2'b01; + else if ((Rs2E == RdM) & FWriteIntM) ForwardBE = 2'b11; end // Stall on dependent operations that finish in Mem Stage and can't bypass in time diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 53bf6f3e1..8b1993be4 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -43,6 +43,8 @@ module ieu ( input logic DataMisalignedM, input logic DataAccessFaultM, input logic SquashSCW, + input logic FWriteIntM, + input logic [`XLEN-1:0] FWriteDataM, output logic [1:0] MemRWM, output logic [1:0] AtomicM, output logic [`XLEN-1:0] MemAdrM, WriteDataM, diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 5164a1f1e..cb4a60a81 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -98,7 +98,7 @@ module wallypipelinedhart ( logic [`XLEN-1:0] FWriteDataM; logic SquashSCW; logic FStallD; - logic FWriteIntW; + logic FWriteIntW, FWriteIntM; logic [31:0] FSROutW; logic DivSqrtDoneE; logic IllegalFPUInstrD, IllegalFPUInstrE; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index cb4001504..b795f1a88 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -119,7 +119,6 @@ string tests32f[] = '{ }; string tests64d[] = '{ - "rv64d/I-FMV-D-X-01", "2000", // "rv64d/I-FADD-D-01", "2000", // "rv64d/I-FCLASS-D-01", "2000", // "rv64d/I-FCVT-D-L-01", "2000", @@ -135,7 +134,7 @@ string tests32f[] = '{ // "rv64d/I-FDIV-D-01", "2000", // "rv64d/I-FEQ-D-01", "2000", "rv64d/I-FSD-01", "2000", - "rv64d/I-FLD-01", "2420" + "rv64d/I-FLD-01", "2420", // "rv64d/I-FLE-D-01", "2000", // "rv64d/I-FLT-D-01", "2000", // "rv64d/I-FMADD-D-01", "2000", @@ -143,7 +142,8 @@ string tests32f[] = '{ // "rv64d/I-FMIN-D-01", "2000", // "rv64d/I-FMSUB-D-01", "2000", // "rv64d/I-FMUL-D-01", "2000", - // "rv64d/I-FMV-X-D-01", "2000", + "rv64d/I-FMV-D-X-01", "2000", + "rv64d/I-FMV-X-D-01", "2000" // "rv64d/I-FNMADD-D-01", "2000", // "rv64d/I-FNMSUB-D-01", "2000", // "rv64d/I-FSGNJ-D-01", "2000", @@ -873,8 +873,8 @@ module instrNameDecTB( else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU"; else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W"; else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X"; - else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE - else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE + else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE + else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE else if (funct7[6:2] == 5'b00100) name = "FSGNJ"; else if (funct7[6:2] == 5'b00101) name = "FMIN"; else if (funct7[6:2] == 5'b10100) name = "FLE";