From 0396181d1efbc9c2e518a7628f051f9bab647464 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Wed, 31 Jul 2024 11:00:44 -0500
Subject: [PATCH] Added function to set SPI clock speed.

---
 fpga/zsbl/spi.c | 7 ++++++-
 fpga/zsbl/spi.h | 5 +----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c
index cbb9fa2eb..b8829b12e 100644
--- a/fpga/zsbl/spi.c
+++ b/fpga/zsbl/spi.c
@@ -83,8 +83,13 @@ uint64_t spi_read64() {
   return r;
 }
 
+void spi_set_clock(uint32_t clkin, uint32_t clkout) {
+  uint32_t div = (clkin/(2*clkout)) - 1;
+  write_reg(SPI_SCKDIV, div);
+}
+
 // Initialize Sifive FU540 based SPI Controller
-void spi_init() {
+void spi_init(uint32_t clkin) {
   // Enable interrupts
   write_reg(SPI_IE, 0x3);
 
diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h
index bc85c768f..a662fce86 100644
--- a/fpga/zsbl/spi.h
+++ b/fpga/zsbl/spi.h
@@ -44,10 +44,6 @@
 #define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
 #define SIFIVE_SPI_CSMODE_MODE_OFF       3U
 
-
-#define WAITTX while(!(read_reg(SPI_IP) & 1) {}
-#define WAITRX while(read_reg(SPI_IP) & 2) {}
-
 // inline void write_reg(uintptr_t addr, uint32_t value);
 //inline uint32_t read_reg(uintptr_t addr);
 //inline void spi_sendbyte(uint8_t byte);
@@ -57,6 +53,7 @@ uint8_t spi_txrx(uint8_t byte);
 //inline uint8_t spi_readbyte();
 uint64_t spi_read64();
 void spi_init();
+void spi_set_clock(uint32_t clkin, uint32_t clkout);
 
 static inline void write_reg(uintptr_t addr, uint32_t value) {
   volatile uint32_t * loc = (volatile uint32_t *) addr;