Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

cachereplacementpolicy cleanup

Browse Source
This commit is contained in:
David Harris 2022-02-03 17:18:48 +00:00
parent 65f3bf4e0a
commit 034ff5462c
1 changed files with 30 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

94
pipelined/src/cache/cachereplacementpolicy.sv vendored
View File

@ -53,55 +53,37 @@ module cachereplacementpolicy
logic [INDEXLEN-1:0] RAdrD; logic [INDEXLEN-1:0] RAdrD;
logic LRUWriteEnD; logic LRUWriteEnD;
/* verilator lint_off BLKLOOPINIT */ initial begin
always_ff @(posedge clk) begin assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported");
if (reset) begin
RAdrD <= '0;
PAdrD <= '0;
LRUWriteEnD <= 0;
NewReplacementD <= '0;
for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] <= '0;
end else begin
RAdrD <= RAdr;
PAdrD <= PAdr;
LRUWriteEnD <= LRUWriteEn;
NewReplacementD <= NewReplacement;
if (LRUWriteEnD) begin
ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
end end
end
end
/* verilator lint_on BLKLOOPINIT */
// Pipeline Delay Registers
flopr #(INDEXLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD);
flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr, PAdrD);
flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD);
flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD);
// Replacement Bits: Register file
// Needs to be resettable for simulation, but could omit reset for synthesis ***
always_ff @(posedge clk)
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0;
else if (LRUWriteEnD) ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD;
assign LineReplacementBits = ReplacementBits[RAdrD]; assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index; genvar index;
if(NUMWAYS == 2) begin : TwoWay if(NUMWAYS == 2) begin : PseudoLRU
assign LRUEn[0] = 1'b0; assign LRUEn[0] = 1'b0;
assign NewReplacement[0] = WayHit[1]; assign NewReplacement[0] = WayHit[1];
assign VictimWay[1] = ~LineReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[0];
assign VictimWay[0] = LineReplacementBits[0]; assign VictimWay[0] = LineReplacementBits[0];
end else if (NUMWAYS == 4) begin : PseudoLRU
end else if (NUMWAYS == 4) begin : FourWay // 1 hot encoding for VictimWay; LRU = LineReplacementBits
//| LRU 2 | LRU 1 | LRU 0 | VictimWay
//+-------+-------+-------+-----------
// VictimWay is a function only of the current value of the LRU. //| 1 | - | 1 | 0001
// binary encoding //| 1 | - | 0 | 0010
//assign VictimWay[0] = LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0]; //| 0 | 1 | - | 0100
//assign VictimWay[1] = LineReplacementBits[2]; //| 0 | 0 | - | 1000
// 1 hot encoding
//| WayHit | LRU 2 | LRU 1 | LRU 0 |
//|--------+-------+-------+-------|
//| 0000 | - | - | - |
//| 0001 | 1 | - | 1 |
//| 0010 | 1 | - | 0 |
//| 0100 | 0 | 1 | - |
//| 1000 | 0 | 0 | - |
assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0]; assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
@ -118,32 +100,10 @@ module cachereplacementpolicy
assign LRUMask[1] = WayHit[2]; assign LRUMask[1] = WayHit[2];
assign LRUMask[0] = WayHit[0]; assign LRUMask[0] = WayHit[0];
/* -----\/----- EXCLUDED -----\/----- mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement);
end
// selects /* *** 8-way not yet working - look for a general way to write this for all NUMWAYS
assign LRUEn[2] = 1'b1; else if (NUMWAYS == 8) begin : PseudoLRU
assign LRUEn[1] = WayHit[3];
assign LRUEn[0] = WayHit[3] | WayHit[2];
// mask
assign LRUMask[0] = WayHit[1];
assign LRUMask[1] = WayHit[3];
assign LRUMask[2] = WayHit[3] | WayHit[2];
-----/\----- EXCLUDED -----/\----- */
for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
/* -----\/----- EXCLUDED -----\/-----
assign EncVicWay[1] = LineReplacementBits[2];
assign EncVicWay[0] = LineReplacementBits[2] ? LineReplacementBits[0] : LineReplacementBits[1];
onehotdecoder #(2)
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
-----/\----- EXCLUDED -----/\----- */
end else if (NUMWAYS == 8) begin : EightWay
// selects // selects
assign LRUEn[6] = 1'b1; assign LRUEn[6] = 1'b1;
@ -176,7 +136,7 @@ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBi
waydec(.bin(EncVicWay), waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3], .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]})); VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end end */
endmodule endmodule