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Lint fixes for no priv mode configs

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Jordan Carlin 2024-06-26 22:15:18 -07:00
parent 47e67e99ff
commit 032de34dbd
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3 changed files with 6 additions and 0 deletions
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2
src/privileged/csr.sv
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@ -259,6 +259,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign SCOUNTEREN_REGW = '0; assign SCOUNTEREN_REGW = '0;
assign SATP_REGW = '0; assign SATP_REGW = '0;
assign IllegalCSRSAccessM = 1'b1; assign IllegalCSRSAccessM = 1'b1;
assign STimerInt = '0;
assign SENVCFG_REGW = '0;
end end
// Floating Point CSRs in User Mode only needed if Floating Point is supported // Floating Point CSRs in User Mode only needed if Floating Point is supported

1
src/privileged/csri.sv
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@ -73,6 +73,7 @@ module csri import cvw::*; #(parameter cvw_t P) (
assign MIP_WRITE_MASK = 12'h000; assign MIP_WRITE_MASK = 12'h000;
assign SIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000;
assign MIE_WRITE_MASK = 12'h888; assign MIE_WRITE_MASK = 12'h888;
assign STIP = '0;
end end
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) MIP_REGW_writeable <= 12'b0; if (reset) MIP_REGW_writeable <= 12'b0;

3
src/privileged/csrm.sv
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@ -195,6 +195,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
end end
end else begin
assign MENVCFG_REGW = '0;
assign MENVCFGH_REGW = '0;
end end
// Read machine mode CSRs // Read machine mode CSRs