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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

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This commit is contained in:
Madeleine Masser-Frye 2022-06-10 21:11:47 +00:00
commit 032385aee3
54 changed files with 6037 additions and 249 deletions
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4
.gitignore vendored
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@ -107,4 +107,6 @@ pipelined/config/rv64ic_orig
synthDC/Summary.csv
pipelined/srt/exptestgen
pipelined/srt/testgen
pipelined/srt/qst2
pipelined/srt/qslc_r4a2
pipelined/srt/qslc_r4a2.sv
pipelined/srt/testvectors

4
pipelined/config/buildroot/wally-config.vh
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@ -63,10 +63,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/fpga/wally-config.vh
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@ -65,10 +65,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv32e/wally-config.vh
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@ -66,10 +66,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv32gc/wally-config.vh
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@ -64,10 +64,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv32i/wally-config.vh
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@ -66,10 +66,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv32ic/wally-config.vh
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@ -64,10 +64,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv64BP/wally-config.vh
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@ -66,10 +66,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64

4
pipelined/config/rv64fp/wally-config.vh
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@ -66,10 +66,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv64fpquad/wally-config.vh
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@ -65,10 +65,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv64gc/wally-config.vh
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@ -65,10 +65,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv64i/wally-config.vh
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@ -65,10 +65,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

4
pipelined/config/rv64ic/wally-config.vh
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@ -65,10 +65,10 @@
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 256
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 256
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4

2
pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv32gc arch32f"
vsim -do "do wally-pipelined.do rv32gc arch32i"

4
pipelined/regression/wave.do
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@ -6,7 +6,7 @@ add wave -noupdate /testbench/reset_ext
add wave -noupdate /testbench/memfilename
add wave -noupdate /testbench/dut/core/SATP_REGW
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
@ -468,7 +468,7 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck

22
pipelined/src/uncore/ram.sv
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@ -53,18 +53,18 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic [31:0] HADDRD, RamAddr;
//logic prevHREADYRam, risingHREADYRam;
logic initTrans;
logic memwrite, memwriteD;
logic memwrite, memwriteD, memread;
logic nextHREADYRam;
//logic [3:0] busycount;
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(ByteMask));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); // *** add burst support, or disable on busy
assign memwrite = initTrans & HWRITE;
// *** this seems like a weird way to use reset
flopen #(1) memwritereg(HCLK, initTrans | ~HRESETn, memwrite, memwriteD); // probably drop ~HRESETn in all this
flopen #(32) haddrreg(HCLK, initTrans | ~HRESETn, HADDR, HADDRD);
assign initTrans = HREADY & HSELRam & (HTRANS[1]);
assign memwrite = initTrans & HWRITE; // *** why is initTrans needed? See CLINT interface
assign memread = initTrans & ~HWRITE;
flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD);
flopenr #(32) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
/* // busy FSM to extend READY signal
always @(posedge HCLK, negedge HRESETn)
@ -85,7 +85,9 @@ module ram #(parameter BASE=0, RANGE = 65535) (
end */
assign nextHREADYRam = ~(memwriteD & ~memwrite);
// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
assign nextHREADYRam = ~(memwriteD & memread);
// assign nextHREADYRam = ~(memwriteD & ~memwrite);
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
// assign HREADYRam = ~(memwriteD & ~memwrite);
assign HRESPRam = 0; // OK
@ -109,8 +111,8 @@ module ram #(parameter BASE=0, RANGE = 65535) (
// On writes, use address delayed by one cycle to sync with HWDATA
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD, RamAddr);
// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)

2
pipelined/src/uncore/uncore.sv
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@ -92,7 +92,7 @@ module uncore (
// generate
// on-chip RAM
if (`RAM_SUPPORTED) begin : ram
ram_orig #(
ram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK, .HRESETn,
.HSELRam, .HADDR,

19
pipelined/srt/Makefile
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@ -1,16 +1,19 @@
all: sqrttestgen testgen qst2
all: exptestgen testgen qslc_r4a2
sqrttestgen: sqrttestgen.c
gcc sqrttestgen.c -lm -o sqrttestgen
gcc sqrttestgen.c -o sqrttestgen -lm
testgen: testgen.c
gcc testgen.c -lm -o testgen
qst2: qst2.c
gcc qst2.c -lm -o qst2
gcc -lm -o testgen testgen.c
gcc testgen.c -o testgen -lm
./testgen
exptestgen: exptestgen.c
gcc -lm -o exptestgen exptestgen.c
gcc -o exptestgen exptestgen.c -lm
./exptestgen
qslc_r4a2: qslc_r4a2.c
gcc qslc_r4a2.c -o qslc_r4a2 -lm
./qslc_r4a2 > qslc_r4a2.sv
clean:
rm -f testgen exptestgen qslc_r4a2

198
pipelined/srt/qslc_r4a2.c Normal file
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@ -0,0 +1,198 @@
/*
Program: qslc_r4a2.c
Description: Prints out Quotient Selection Table (assumes CPA is utilized to reduce memory)
User: James E. Stine
*/
#include <stdio.h>
#include <math.h>
#define DIVISOR_SIZE 3
#define CARRY_SIZE 7
#define SUM_SIZE 7
#define TOT_SIZE 7
void disp_binary(double, int, int);
struct bits {
unsigned int divisor : DIVISOR_SIZE;
int tot : TOT_SIZE;
} pla;
/*
Function: disp_binary
Description: This function displays a Double-Precision number into
four 16 bit integers using the global union variable
dp_number
Argument List: double x The value to be converted
int bits_to_left Number of bits left of radix point
int bits_to_right Number of bits right of radix point
Return value: none
*/
void disp_binary(double x, int bits_to_left, int bits_to_right) {
int i;
double diff;
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
printf("0");
}
if (i == bits_to_right+1)
;
return;
}
if (x < 0.0)
x = pow(2.0, ((double) bits_to_left)) + x;
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
diff = pow(2.0, ((double) -i) );
if (x < diff)
printf("0");
else {
printf("1");
x -= diff;
}
if (i == 0)
;
}
}
int main() {
int m;
int n;
int o;
pla.divisor = 0;
pla.tot = 0;
printf("\tcase({D[5:3],Wmsbs})\n");
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
printf("\t\t10'b");
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
printf("_");
disp_binary((double) pla.tot, TOT_SIZE, 0);
printf(": q = 4'b");
/*
4 bits for Radix 4 (a=2)
1000 = +2
0100 = +1
0000 = 0
0010 = -1
0001 = -2
*/
switch (pla.divisor) {
case 0:
if ((pla.tot) >= 12)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -4)
printf("0000");
else if ((pla.tot) >= -13)
printf("0010");
else
printf("0001");
break;
case 1:
if ((pla.tot) >= 14)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -15)
printf("0010");
else
printf("0001");
break;
case 2:
if ((pla.tot) >= 15)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -16)
printf("0010");
else
printf("0001");
break;
case 3:
if ((pla.tot) >= 16)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -18)
printf("0010");
else
printf("0001");
break;
case 4:
if ((pla.tot) >= 18)
printf("1000");
else if ((pla.tot) >= 6)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -20)
printf("0010");
else
printf("0001");
break;
case 5:
if ((pla.tot) >= 20)
printf("1000");
else if ((pla.tot) >= 6)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -20)
printf("0010");
else
printf("0001");
break;
case 6:
if ((pla.tot) >= 20)
printf("1000");
else if ((pla.tot) >= 8)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -22)
printf("0010");
else
printf("0001");
break;
case 7:
if ((pla.tot) >= 24)
printf("1000");
else if ((pla.tot) >= 8)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -24)
printf("0010");
else
printf("0001");
break;
default: printf ("XXX");
}
printf(";\n");
(pla.tot)++;
}
(pla.divisor)++;
}
printf("\tendcase\n");
}

201
pipelined/srt/qst2.c
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@ -1,201 +0,0 @@
/*
Program: qst2.c
Description: Prints out QST (assumes CPA is utilized to reduce memory)
User: James E. Stine
*/
#include <stdio.h>
#include <math.h>
#define DIVISOR_SIZE 3
#define CARRY_SIZE 7
#define SUM_SIZE 7
#define TOT_SIZE 7
void disp_binary(double, int, int);
struct bits {
unsigned int divisor : DIVISOR_SIZE;
int tot : TOT_SIZE;
} pla;
/*
Function: disp_binary
Description: This function displays a Double-Precision number into
four 16 bit integers using the global union variable
dp_number
Argument List: double x The value to be converted
int bits_to_left Number of bits left of radix point
int bits_to_right Number of bits right of radix point
Return value: none
*/
void disp_binary(double x, int bits_to_left, int bits_to_right) {
int i;
double diff;
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
printf("0");
}
if (i == bits_to_right+1)
printf(" ");
return;
}
if (x < 0.0)
x = pow(2.0, ((double) bits_to_left)) + x;
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
diff = pow(2.0, ((double) -i) );
if (x < diff)
printf("0");
else {
printf("1");
x -= diff;
}
if (i == 0)
printf(" ");
}
}
int main() {
int m;
int n;
int o;
pla.divisor = 0;
pla.tot = 0;
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
disp_binary((double) pla.tot, TOT_SIZE, 0);
/*
4 bits for Radix 4 (a=2)
1000 = +2
0100 = +1
0000 = 0
0010 = -1
0001 = -2
*/
switch (pla.divisor) {
case 0:
if ((pla.tot) >= 12)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -4)
printf(" 0000");
else if ((pla.tot) >= -13)
printf(" 0010");
else
printf(" 0001");
break;
case 1:
if ((pla.tot) >= 14)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -15)
printf(" 0010");
else
printf(" 0001");
break;
case 2:
if ((pla.tot) >= 15)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -16)
printf(" 0010");
else
printf(" 0001");
break;
case 3:
if ((pla.tot) >= 16)
printf(" 1000");
else if ((pla.tot) >= 4)
printf(" 0100");
else if ((pla.tot) >= -6)
printf(" 0000");
else if ((pla.tot) >= -18)
printf(" 0010");
else
printf(" 0001");
break;
case 4:
if ((pla.tot) >= 18)
printf(" 1000");
else if ((pla.tot) >= 6)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -20)
printf(" 0010");
else
printf(" 0001");
break;
case 5:
if ((pla.tot) >= 20)
printf(" 1000");
else if ((pla.tot) >= 6)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -20)
printf(" 0010");
else
printf(" 0001");
break;
case 6:
if ((pla.tot) >= 20)
printf(" 1000");
else if ((pla.tot) >= 8)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -22)
printf(" 0010");
else
printf(" 0001");
break;
case 7:
if ((pla.tot) >= 24)
printf(" 1000");
else if ((pla.tot) >= 8)
printf(" 0100");
else if ((pla.tot) >= -8)
printf(" 0000");
else if ((pla.tot) >= -24)
printf(" 0010");
else
printf(" 0001");
break;
default:
printf (" XXX");
}
printf("\n");
(pla.tot)++;
}
(pla.divisor)++;
}
}

1
pipelined/srt/stine/README Executable file
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@ -0,0 +1 @@
vsim -do iter64.do -c

22
pipelined/srt/stine/README.md Executable file
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@ -0,0 +1,22 @@
This is a novel integer divider using r4 division by recurrence. The
reference is:
J. E. Stine and K. Hill, "An Efficient Implementation of Radix-4
Integer Division Using Scaling," 2020 IEEE 63rd International Midwest
Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA,
2020, pp. 1092-1095, doi: 10.1109/MWSCAS48704.2020.9184631.
Although this version does not contain scaling, it could do this, if
needed. Moreover, a higher radix or overlapped radix can be done
easily to expand the the size. Also, the implementations here are
initially unsigned but hope to expand for signed, which should be
easy.
There are two types of tests in this directory within each testbench.
One tests for 32-bits and the other 64-bits:
int32div.do and int64div.do = test individual vector for debugging
iter32.do and iter64.do = do not use any waveform generation and just
output lots of tests

19
pipelined/srt/stine/checkme.sh Executable file
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@ -0,0 +1,19 @@
#!/bin/sh
cat iter64_signed.out | grep "0 1$"
cat iter64_signed.out | grep "1 0$"
cat iter64_signed.out | grep "0 0$"
cat iter64_unsigned.out | grep "0 1$"
cat iter64_unsigned.out | grep "1 0$"
cat iter64_unsigned.out | grep "0 0$"
cat iter32_signed.out | grep "0 1$"
cat iter32_signed.out | grep "1 0$"
cat iter32_signed.out | grep "0 0$"
cat iter32_unsigned.out | grep "0 1$"
cat iter32_unsigned.out | grep "1 0$"
cat iter32_unsigned.out | grep "0 0$"
cat iter128_signed.out | grep "0 1$"
cat iter128_signed.out | grep "1 0$"
cat iter128_signed.out | grep "0 0$"
cat iter128_unsigned.out | grep "0 1$"
cat iter128_unsigned.out | grep "1 0$"
cat iter128_unsigned.out | grep "0 0$"

27
pipelined/srt/stine/idiv-config.vh Normal file
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//////////////////////////////////////////
// wally-config.vh
//
// Written: james.stine@okstate.edu 9 June 2022
// Modified:
//
// Purpose: Specify which features are configured
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// Integer division tests
`define IDIV_TESTS 1048576

2802
pipelined/srt/stine/intdiv.sv Executable file
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50
pipelined/srt/stine/iter128.do Normal file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

50
pipelined/srt/stine/iter128S.do Normal file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128S.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

50
pipelined/srt/stine/iter32.do Executable file
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@ -0,0 +1,50 @@
# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

50
pipelined/srt/stine/iter32S.do Normal file
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@ -0,0 +1,50 @@
# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32S.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

50
pipelined/srt/stine/iter64.do Executable file
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@ -0,0 +1,50 @@
# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

50
pipelined/srt/stine/iter64S.do Normal file
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@ -0,0 +1,50 @@
# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64S.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 999586700ns
quit

182
pipelined/srt/stine/lod.sv Executable file
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///////////////////////////////////////////
// lod.sv
//
// Written: James.Stine@okstate.edu 1 February 2021
// Modified:
//
// Purpose: Integer Divide instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
module lod2 (P, V, B);
input logic [1:0] B;
output logic P;
output logic V;
assign V = B[0] | B[1];
assign P = B[0] & ~B[1];
endmodule // lo2
module lod_hier #(parameter WIDTH=8)
(input logic [WIDTH-1:0] B,
output logic [$clog2(WIDTH)-1:0] ZP,
output logic ZV);
if (WIDTH == 128)
lod128 lod128 (ZP, ZV, B);
else if (WIDTH == 64)
lod64 lod64 (ZP, ZV, B);
else if (WIDTH == 32)
lod32 lod32 (ZP, ZV, B);
else if (WIDTH == 16)
lod16 lod16 (ZP, ZV, B);
else if (WIDTH == 8)
lod8 lod8 (ZP, ZV, B);
else if (WIDTH == 4)
lod4 lod4 (ZP, ZV, B);
endmodule // lod_hier
module lod4 (ZP, ZV, B);
input logic [3:0] B;
logic ZPa;
logic ZPb;
logic ZVa;
logic ZVb;
output logic [1:0] ZP;
output logic ZV;
lod2 l1(ZPa, ZVa, B[1:0]);
lod2 l2(ZPb, ZVb, B[3:2]);
assign ZP[0:0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod4
module lod8 (ZP, ZV, B);
input logic [7:0] B;
logic [1:0] ZPa;
logic [1:0] ZPb;
logic ZVa;
logic ZVb;
output logic [2:0] ZP;
output logic ZV;
lod4 l1(ZPa, ZVa, B[3:0]);
lod4 l2(ZPb, ZVb, B[7:4]);
assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod8
module lod16 (ZP, ZV, B);
input logic [15:0] B;
logic [2:0] ZPa;
logic [2:0] ZPb;
logic ZVa;
logic ZVb;
output logic [3:0] ZP;
output logic ZV;
lod8 l1(ZPa, ZVa, B[7:0]);
lod8 l2(ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod16
module lod32 (ZP, ZV, B);
input logic [31:0] B;
logic [3:0] ZPa;
logic [3:0] ZPb;
logic ZVa;
logic ZVb;
output logic [4:0] ZP;
output logic ZV;
lod16 l1(ZPa, ZVa, B[15:0]);
lod16 l2(ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod32
module lod64 (ZP, ZV, B);
input logic [63:0] B;
logic [4:0] ZPa;
logic [4:0] ZPb;
logic ZVa;
logic ZVb;
output logic [5:0] ZP;
output logic ZV;
lod32 l1(ZPa, ZVa, B[31:0]);
lod32 l2(ZPb, ZVb, B[63:32]);
assign ZP[4:0] = ZVb ? ZPb : ZPa;
assign ZP[5] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod64
module lod128 (ZP, ZV, B);
input logic [127:0] B;
logic [5:0] ZPa;
logic [5:0] ZPb;
logic ZVa;
logic ZVb;
output logic [6:0] ZP;
output logic ZV;
lod64 l1(ZPa, ZVa, B[63:0]);
lod64 l2(ZPb, ZVb, B[127:64]);
assign ZP[5:0] = ZVb ? ZPb : ZPa;
assign ZP[6] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lod128

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pipelined/srt/stine/lzd.do Executable file
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# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog lod.sv lzd_tb.sv
# start and run simulation
vsim -voptargs=+acc work.stimulus
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /stimulus/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 350
configure wave -valuecolwidth 200
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 800ns
quit

182
pipelined/srt/stine/lzd.sv Executable file
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///////////////////////////////////////////
// lzd.sv
//
// Written: James.Stine@okstate.edu 1 February 2021
// Modified:
//
// Purpose: Integer Divide instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
module lzd2 (P, V, B);
input logic [1:0] B;
output logic P;
output logic V;
assign V = ~(B[0] & B[1]);
assign P = B[1];
endmodule // lzd2
module lzd_hier #(parameter WIDTH=8)
(input logic [WIDTH-1:0] B,
output logic [$clog2(WIDTH)-1:0] ZP,
output logic ZV);
if (WIDTH == 128)
lzd128 lzd127 (ZP, ZV, B);
else if (WIDTH == 64)
lzd64 lzd64 (ZP, ZV, B);
else if (WIDTH == 32)
lzd32 lzd32 (ZP, ZV, B);
else if (WIDTH == 16)
lzd16 lzd16 (ZP, ZV, B);
else if (WIDTH == 8)
lzd8 lzd8 (ZP, ZV, B);
else if (WIDTH == 4)
lzd4 lzd4 (ZP, ZV, B);
endmodule // lzd_hier
module lzd4 (ZP, ZV, B);
input logic [3:0] B;
logic ZPa;
logic ZPb;
logic ZVa;
logic ZVb;
output logic [1:0] ZP;
output logic ZV;
lzd2 l1 (ZPa, ZVa, B[1:0]);
lzd2 l2 (ZPb, ZVb, B[3:2]);
assign ZP[0:0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd4
module lzd8 (ZP, ZV, B);
input logic [7:0] B;
logic [1:0] ZPa;
logic [1:0] ZPb;
logic ZVa;
logic ZVb;
output logic [2:0] ZP;
output logic ZV;
lzd4 l1 (ZPa, ZVa, B[3:0]);
lzd4 l2 (ZPb, ZVb, B[7:4]);
assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd8
module lzd16 (ZP, ZV, B);
input logic [15:0] B;
logic [2:0] ZPa;
logic [2:0] ZPb;
logic ZVa;
logic ZVb;
output logic [3:0] ZP;
output logic ZV;
lzd8 l1 (ZPa, ZVa, B[7:0]);
lzd8 l2 (ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd16
module lzd32 (ZP, ZV, B);
input logic [31:0] B;
logic [3:0] ZPa;
logic [3:0] ZPb;
logic ZVa;
logic ZVb;
output logic [4:0] ZP;
output logic ZV;
lzd16 l1 (ZPa, ZVa, B[15:0]);
lzd16 l2 (ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd32
module lzd64 (ZP, ZV, B);
input logic [63:0] B;
logic [4:0] ZPa;
logic [4:0] ZPb;
logic ZVa;
logic ZVb;
output logic [5:0] ZP;
output logic ZV;
lzd32 l1 (ZPa, ZVa, B[31:0]);
lzd32 l2 (ZPb, ZVb, B[63:32]);
assign ZP[4:0] = ZVb ? ZPb : ZPa;
assign ZP[5] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd64
module lzd128 (ZP, ZV, B);
input logic [127:0] B;
logic [5:0] ZPa;
logic [5:0] ZPb;
logic ZVa;
logic ZVb;
output logic [6:0] ZP;
output logic ZV;
lzd64 l1 (ZPa, ZVa, B[64:0]);
lzd64 l2 (ZPb, ZVb, B[127:63]);
assign ZP[5:0] = ZVb ? ZPb : ZPa;
assign ZP[6] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd128

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pipelined/srt/stine/lzd_tb.sv Executable file
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//
// File name : tb
// Title : test
// project : HW3
// Library : test
// Purpose : definition of modules for testbench
// notes :
//
// Copyright Oklahoma State University
//
// Top level stimulus module
`timescale 1ns/1ps
module stimulus;
logic [7:0] B;
logic [2:0] ZP;
logic ZV;
logic clk;
integer handle3;
integer desc3;
integer i;
// instatiate part to test
lzd_hier #(8) dut (B, ZP, ZV);
initial
begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("lzd.out");
desc3 = handle3;
end
initial
begin
for (i=0; i < 256; i=i+1)
begin
// Put vectors before beginning of clk
@(posedge clk)
begin
B = $random;
end
@(negedge clk)
begin
$fdisplay(desc3, "%b || %b %b", B, ZP, ZV);
end
end // for (i=0; i < 256; i=i+1)
$finish;//
end // initial begin
endmodule // stimulus

51
pipelined/srt/stine/mux.sv Executable file
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module mux2 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule // mux2
module mux3 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule // mux3
module mux4 #(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule // mux4
module mux21x32 (Z, A, B, Sel);
input logic [31:0] A;
input logic [31:0] B;
input logic Sel;
output logic [31:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x32
module mux21x64 (Z, A, B, Sel);
input logic [63:0] A;
input logic [63:0] B;
input logic Sel;
output logic [63:0] Z;
assign Z = Sel ? B : A;
endmodule // mux21x64

23
pipelined/srt/stine/otf4.in Normal file
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.i 4
.o 6
.ilb quot[3] quot[2] quot[1] quot[0]
.ob Qin[1] Qin[0] QMin[1] QMin[0] CshiftQ CshiftQM
0000 001100
0001 100110
0010 111010
0011 ------
0100 010001
0101 ------
0110 ------
0111 ------
1000 100101
1001 ------
1010 ------
1011 ------
1100 ------
1101 ------
1110 ------
1111 ------
.e

BIN
pipelined/srt/stine/qslc_r4a2 Executable file
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198
pipelined/srt/stine/qslc_r4a2.c Normal file
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/*
Program: qslc_r4a2.c
Description: Prints out Quotient Selection Table (assumes CPA is utilized to reduce memory)
User: James E. Stine
*/
#include <stdio.h>
#include <math.h>
#define DIVISOR_SIZE 3
#define CARRY_SIZE 7
#define SUM_SIZE 7
#define TOT_SIZE 7
void disp_binary(double, int, int);
struct bits {
unsigned int divisor : DIVISOR_SIZE;
int tot : TOT_SIZE;
} pla;
/*
Function: disp_binary
Description: This function displays a Double-Precision number into
four 16 bit integers using the global union variable
dp_number
Argument List: double x The value to be converted
int bits_to_left Number of bits left of radix point
int bits_to_right Number of bits right of radix point
Return value: none
*/
void disp_binary(double x, int bits_to_left, int bits_to_right) {
int i;
double diff;
if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) {
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
printf("0");
}
if (i == bits_to_right+1)
;
return;
}
if (x < 0.0)
x = pow(2.0, ((double) bits_to_left)) + x;
for (i = -bits_to_left + 1; i <= bits_to_right; i++) {
diff = pow(2.0, ((double) -i) );
if (x < diff)
printf("0");
else {
printf("1");
x -= diff;
}
if (i == 0)
;
}
}
int main() {
int m;
int n;
int o;
pla.divisor = 0;
pla.tot = 0;
printf("\tcase({D[5:3],Wmsbs})\n");
for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) {
for (m=0; m < pow(2.0, TOT_SIZE); m++) {
printf("\t\t10'b");
disp_binary((double) pla.divisor, DIVISOR_SIZE, 0);
printf("_");
disp_binary((double) pla.tot, TOT_SIZE, 0);
printf(": q = 4'b");
/*
4 bits for Radix 4 (a=2)
1000 = +2
0100 = +1
0000 = 0
0010 = -1
0001 = -2
*/
switch (pla.divisor) {
case 0:
if ((pla.tot) >= 12)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -4)
printf("0000");
else if ((pla.tot) >= -13)
printf("0010");
else
printf("0001");
break;
case 1:
if ((pla.tot) >= 14)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -15)
printf("0010");
else
printf("0001");
break;
case 2:
if ((pla.tot) >= 15)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -16)
printf("0010");
else
printf("0001");
break;
case 3:
if ((pla.tot) >= 16)
printf("1000");
else if ((pla.tot) >= 4)
printf("0100");
else if ((pla.tot) >= -6)
printf("0000");
else if ((pla.tot) >= -18)
printf("0010");
else
printf("0001");
break;
case 4:
if ((pla.tot) >= 18)
printf("1000");
else if ((pla.tot) >= 6)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -20)
printf("0010");
else
printf("0001");
break;
case 5:
if ((pla.tot) >= 20)
printf("1000");
else if ((pla.tot) >= 6)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -20)
printf("0010");
else
printf("0001");
break;
case 6:
if ((pla.tot) >= 20)
printf("1000");
else if ((pla.tot) >= 8)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -22)
printf("0010");
else
printf("0001");
break;
case 7:
if ((pla.tot) >= 24)
printf("1000");
else if ((pla.tot) >= 8)
printf("0100");
else if ((pla.tot) >= -8)
printf("0000");
else if ((pla.tot) >= -24)
printf("0010");
else
printf("0001");
break;
default: printf ("XXX");
}
printf(";\n");
(pla.tot)++;
}
(pla.divisor)++;
}
printf("\tendcase\n");
}

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pipelined/srt/stine/run.sh Executable file
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#!/bin/sh
vsim -do iter32S.do -c
vsim -do iter32.do -c
vsim -do iter64.do -c
vsim -do iter64S.do -c
vsim -do iter128.do -c
vsim -do iter128S.do -c

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pipelined/srt/stine/shift.sv Executable file
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///////////////////////////////////////////
// shifters.sv
//
// Written: James.Stine@okstate.edu 1 February 2021
// Modified:
//
// Purpose: Integer Divide instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
module shift_right #(parameter WIDTH=8)
(input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Shift,
output logic [WIDTH-1:0] Z);
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
logic sign;
genvar i;
assign stage[0] = A;
generate
for (i=0;i<$clog2(WIDTH);i=i+1)
begin : genbit
mux2 #(WIDTH) mux_inst (stage[i],
{{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]},
Shift[$clog2(WIDTH)-i-1],
stage[i+1]);
end
endgenerate
assign Z = stage[$clog2(WIDTH)];
endmodule // shift_right
module shift_left #(parameter WIDTH=8)
(input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Shift,
output logic [WIDTH-1:0] Z);
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
genvar i;
assign stage[0] = A;
generate
for (i=0;i<$clog2(WIDTH);i=i+1)
begin : genbit
mux2 #(WIDTH) mux_inst (stage[i],
{stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}},
Shift[$clog2(WIDTH)-i-1],
stage[i+1]);
end
endgenerate
assign Z = stage[$clog2(WIDTH)];
endmodule // shift_left

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pipelined/srt/stine/shift_left.do Executable file
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# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv shift.sv shift_left_tb.sv
# start and run simulation
vsim -voptargs=+acc work.stimulus
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /stimulus/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 800ns
quit

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pipelined/srt/stine/shift_left_tb.sv Executable file
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//
// File name : tb
// Title : test
// project : HW3
// Library : test
// Purpose : definition of modules for testbench
// notes :
//
// Copyright Oklahoma State University
//
// Top level stimulus module
`timescale 1ns/1ps
`define XLEN 32
module stimulus;
logic [`XLEN-1:0] A;
logic [$clog2(`XLEN)-1:0] Shift;
logic [`XLEN-1:0] Z;
logic [`XLEN-1:0] Z_corr;
//logic [63:0] A;
//logic [5:0] Shift;
//logic [63:0] Z;
//logic [63:0] Z_corr;
//logic [63:0] Z_orig;
logic clk;
integer handle3;
integer desc3;
integer i;
// instatiate part to test
shift_left dut1 (A, Shift, Z);
assign Z_corr = (A << Shift);
initial
begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("shift_left.out");
desc3 = handle3;
end
initial
begin
for (i=0; i < 256; i=i+1)
begin
// Put vectors before beginning of clk
@(posedge clk)
begin
A = $random;
Shift = $random;
end
@(negedge clk)
begin
$fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
end
end // for (i=0; i < 256; i=i+1)
$finish;//
end // initial begin
endmodule // stimulus

55
pipelined/srt/stine/shift_right.do Executable file
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# Copyright 1991-2016 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv shift.sv shift_right_tb.sv
# start and run simulation
vsim -voptargs=+acc work.stimulus
view wave
-- display input and output signals as hexidecimal values
# Diplays All Signals recursively
add wave -hex -r /stimulus/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 800ns
quit

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pipelined/srt/stine/shift_right_tb.sv Executable file
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//
// File name : tb
// Title : test
// project : HW3
// Library : test
// Purpose : definition of modules for testbench
// notes :
//
// Copyright Oklahoma State University
//
// Top level stimulus module
`timescale 1ns/1ps
`define XLEN 32
module stimulus;
logic [`XLEN-1:0] A;
logic [$clog2(`XLEN)-1:0] Shift;
logic [`XLEN-1:0] Z;
logic [`XLEN-1:0] Z_corr;
logic clk;
integer handle3;
integer desc3;
integer i;
// instatiate part to test
shift_right dut1 (A, Shift, Z);
assign Z_corr = (A >> Shift);
initial
begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("shift_right.out");
desc3 = handle3;
#250 $finish;
end
initial
begin
for (i=0; i < 128; i=i+1)
begin
// Put vectors before beginning of clk
@(posedge clk)
begin
A = $random;
Shift = $random;
end
@(negedge clk)
begin
$fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
end
end // @(negedge clk)
end // for (j=0; j < 32; j=j+1)
endmodule // stimulus

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pipelined/srt/stine/shifter.sv Executable file
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module shifter_right(input logic signed [63:0] a,
input logic [ 5:0] shamt,
output logic signed [63:0] y);
y = a >> shamt;
endmodule // shifter_right
module shifter_left(input logic signed [63:0] a,
input logic [ 5:0] shamt,
output logic signed [63:0] y);
y = a << shamt;
endmodule // shifter_right

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pipelined/srt/stine/test_iter128.sv Normal file
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`include "idiv-config.vh"
module tb;
logic [127:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [127:0] Q;
logic [127:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [127:0] Ncomp;
logic [127:0] Dcomp;
logic [127:0] Qcomp;
logic [127:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter128_unsigned.out");
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 128'h0;
#0 D = 128'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = {$urandom(), $urandom(), $urandom(), $urandom()};
D = {$urandom(), $urandom(), $urandom(), $urandom()};
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
vectornum = vectornum + 1;
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

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pipelined/srt/stine/test_iter128S.sv Normal file
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`include "idiv-config.vh"
module tb;
logic [127:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [127:0] Q;
logic [127:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [31:0] rnd1;
logic [31:0] rnd2;
logic [127:0] Ncomp;
logic [127:0] Dcomp;
logic [127:0] Qcomp;
logic [127:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter128_signed.out");
end
/*
// VCD generation for power estimation
initial
begin
$dumpfile("iter128_signed.vcd");
$dumpvars (0,tb.dut);
end
*/
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b1;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 128'h0;
#0 D = 128'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = {$urandom(), $urandom(), $urandom(), $urandom()};
D = {$urandom(), $urandom(), $urandom(), $urandom()};
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (1)
@(posedge clk);
start <= 1'b0;
repeat (65)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = $signed(Ncomp)/$signed(Dcomp);
Rcomp = $signed(Ncomp)%$signed(Dcomp);
vectornum = vectornum + 1;
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

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pipelined/srt/stine/test_iter32.sv Executable file
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`include "idiv-config.vh"
module tb;
logic [31:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [31:0] Q;
logic [31:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [31:0] Ncomp;
logic [31:0] Dcomp;
logic [31:0] Qcomp;
logic [31:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter32_unsigned.out");
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 32'h0;
#0 D = 32'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = $urandom;
D = $urandom;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
vectornum = vectornum + 1;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

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`include "idiv-config.vh"
module tb;
logic [31:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [31:0] Q;
logic [31:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [31:0] Ncomp;
logic [31:0] Dcomp;
logic [31:0] Qcomp;
logic [31:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter32_signed.out");
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b1;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 32'h0;
#0 D = 32'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = $urandom;
D = $urandom;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = $signed(Ncomp)/$signed(Dcomp);
Rcomp = $signed(Ncomp)%$signed(Dcomp);
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
vectornum = vectornum + 1;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

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pipelined/srt/stine/test_iter64.sv Executable file
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`include "idiv-config.vh"
module tb;
logic [63:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [63:0] Q;
logic [63:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [63:0] Ncomp;
logic [63:0] Dcomp;
logic [63:0] Qcomp;
logic [63:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter64_unsigned.out");
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 64'h0;
#0 D = 64'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = {$urandom(), $urandom()};
D = {$urandom(), $urandom()};
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
vectornum = vectornum + 1;
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

79
pipelined/srt/stine/test_iter64S.sv Normal file
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@ -0,0 +1,79 @@
`include "idiv-config.vh"
module tb;
logic [63:0] N, D;
logic clk;
logic reset;
logic start;
logic S;
logic [63:0] Q;
logic [63:0] rem0;
logic div0;
logic done;
integer handle3;
integer desc3;
integer i;
logic [63:0] Ncomp;
logic [63:0] Dcomp;
logic [63:0] Qcomp;
logic [63:0] Rcomp;
logic [31:0] vectornum;
logic [31:0] errors;
intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
vectornum = 0;
errors = 0;
handle3 = $fopen("iter64_signed.out");
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 S = 1'b1;
#0 reset = 1'b1;
#30 reset = 1'b0;
#30 N = 64'h0;
#0 D = 64'h0;
for (i=0; i<`IDIV_TESTS; i=i+1)
begin
N = {$urandom(), $urandom()};
D = {$urandom(), $urandom()};
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = $signed(Ncomp)/$signed(Dcomp);
Rcomp = $signed(Ncomp)%$signed(Dcomp);
if ((Q !== Qcomp)) begin
errors = errors + 1;
end
vectornum = vectornum + 1;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
$display("%d tests completed, %d errors", vectornum, errors);
$finish;
end
endmodule // tb

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4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
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@ -33,7 +33,9 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// Code copied from test library to cause m time interrupt, with time loop replaced with wfi.
li x28, 0x40 // Desired offset from the present time
/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi
instruction begins, then the program might fall into a loop and run forever*/
li x28, 0x50 // Desired offset from the present time
mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles
la x29, 0x02004000 // MTIMECMP register in CLINT
la x30, 0x0200BFF8 // MTIME register in CLINT