diff --git a/.gitignore b/.gitignore index 0d8423d82..3a6dad8b0 100644 --- a/.gitignore +++ b/.gitignore @@ -243,3 +243,4 @@ tests/functcov/* tests/functcov/*/* sim/vcs/simprofile* sim/verilator/verilator.log +/fpga/rvvidaemon/rvvidaemon diff --git a/.gitmodules b/.gitmodules index ca097a125..69054d830 100644 --- a/.gitmodules +++ b/.gitmodules @@ -30,3 +30,7 @@ [submodule "addins/ahbsdc"] path = addins/ahbsdc url = http://github.com/JacobPease/ahbsdc.git +[submodule "addins/verilog-ethernet"] + sparseCheckout = true + path = addins/verilog-ethernet + url = https://github.com/ross144/verilog-ethernet.git diff --git a/addins/README.md b/addins/README.md new file mode 100644 index 000000000..ba04e05eb --- /dev/null +++ b/addins/README.md @@ -0,0 +1,3 @@ +verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. +To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info +This will make the working directory only contain the necessary files. diff --git a/addins/sparse-checkout b/addins/sparse-checkout new file mode 100644 index 000000000..74cc3f25a --- /dev/null +++ b/addins/sparse-checkout @@ -0,0 +1,17 @@ +rtl/eth_mac_mii_fifo.sv +rtl/eth_mac_mii.sv +rtl/mii_phy_if.sv +rtl/ssio_ddr_in.sv +rtl/ssio_sdr_in.sv +rtl/eth_mac_1g.sv +rtl/axis_gmii_rx.sv +rtl/lfsr.sv +rtl/eth_axis_tx.sv +rtl/mac_ctrl_tx.sv +rtl/axis_gmii_tx.sv +rtl/mac_ctrl_rx.sv +rtl/mac_pause_ctrl_tx.sv +rtl/mac_pause_ctrl_rx.sv +lib/axis/rtl/axis_async_fifo_adapter.sv +lib/axis/rtl/axis_adapter.sv +lib/axis/rtl/axis_async_fifo.sv diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet new file mode 160000 index 000000000..43990ab4f --- /dev/null +++ b/addins/verilog-ethernet @@ -0,0 +1 @@ +Subproject commit 43990ab4fd0c8d34dbc1be5cd8d4f3ed3e33f853 diff --git a/config/derivlist.txt b/config/derivlist.txt index 1edd20b7b..01ad315e5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -57,6 +57,10 @@ EXT_MEM_RANGE 64'h0FFFFFFF SDC_SUPPORTED 1 PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 +RVVI_SYNTH_SUPPORTED 0 +RVVI_INIT_TIME_OUT 32'd100000000 +RVVI_PACKET_DELAY 32'd350 + # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 4ec0123d1..1234bbcdf 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index c861759d9..9f5809383 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd2; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 01818afc2..6bfea805e 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 05a8fd242..3918c702c 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index b8ed8dc47..86036aaa7 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 94360877f..0e13f9ea1 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; +// debug tools +localparam logic RVVI_SYNTH_SUPPORTED = 0; +localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; +localparam [31:0] RVVI_PACKET_DELAY = 32'd2; + `include "config-shared.vh" diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index c80b00232..14b5ee45c 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -200,6 +200,9 @@ localparam cvw_t P = '{ DURLEN : DURLEN, DIVb : DIVb, DIVBLEN : DIVBLEN, - INTDIVb : INTDIVb + INTDIVb : INTDIVb, + RVVI_SYNTH_SUPPORTED : RVVI_SYNTH_SUPPORTED, + RVVI_INIT_TIME_OUT : RVVI_INIT_TIME_OUT, + RVVI_PACKET_DELAY : RVVI_PACKET_DELAY }; diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 6fc660e8d..556c75c43 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -9,6 +9,32 @@ set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}] +##### RVVI Ethernet #### +# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc +set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] +set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] +set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] +set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] +set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] +set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] +set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] +set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] +set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] +set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] +set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] +set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] +set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] +set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] +set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] +set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] + +create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk] +create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk] + +set_false_path -to [get_ports {phy_ref_clk phy_reset_n}] +set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}] + ##### GPI #### set_property PACKAGE_PIN A8 [get_ports {GPI[0]}] set_property PACKAGE_PIN C9 [get_ports {GPI[1]}] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 5217067eb..afed3dd23 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -7,3 +7,4 @@ lsu/lsu.sv: logic PAdrM lsu/lsu.sv: logic ReadDataM lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic MemRWM +privileged/csrc.sv: logic HPMCOUNTER_REGW diff --git a/fpga/constraints/small-debug-rvvi.xdc b/fpga/constraints/small-debug-rvvi.xdc new file mode 100644 index 000000000..f8ebbfe0d --- /dev/null +++ b/fpga/constraints/small-debug-rvvi.xdc @@ -0,0 +1,83 @@ +create_debug_core u_ila_0 ila +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN true [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +create_debug_port u_ila_0 trig_in +create_debug_port u_ila_0 trig_in_ack +#set_property port_width 1 [get_debug_ports u_ila_0/trig_in] +#set_property port_width 1 [get_debug_ports u_ila_0/trig_in_ack] +#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/trig_in] +connect_debug_port u_ila_0/trig_in [get_nets IlaTrigger] +#connect_debug_port u_ila_0/trig_in_ack [get_nets IlaTriggerAck] +connect_debug_port u_ila_0/clk [get_nets CPUCLK] + +set_property port_width 32 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list rvvi_synth/RvviAxiWlast ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {rvvi_synth/RvviAxiRlast}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {rvvi_synth/RvviAxiRvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {rvvi_synth/packetizer/CurrState[0]} {rvvi_synth/packetizer/CurrState[1]} {rvvi_synth/packetizer/CurrState[2]} {rvvi_synth/packetizer/CurrState[3]}]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {rvvi_synth/RvviAxiWvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {RVVIStall}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {rvvi_synth/valid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {rvvi_synth/RvviAxiWready}]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {rvvi_synth/triggergen/CurrState[0]} {rvvi_synth/triggergen/CurrState[1]} {rvvi_synth/triggergen/CurrState[2]}]] + + +# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. +#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] +connect_debug_port dbg_hub/clk [get_nets CPUCLK] + diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index df4ed0e2a..c23e22ee0 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -51,6 +51,8 @@ PreProcessFiles: $(MAKE) -C ../../sim deriv rm -rf ../src/CopiedFiles_do_not_add_to_repo/ cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/ + cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi + cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi mkdir ../src/CopiedFiles_do_not_add_to_repo/config/ cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ ./insert_debug_comment.sh diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl index 2f003e7a5..146a9cf41 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/xlnx_mmcm.tcl @@ -12,10 +12,11 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.NUM_OUT_CLKS {3} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_USED {false} \ + CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/fpga/rvvidaemon/Makefile b/fpga/rvvidaemon/Makefile new file mode 100644 index 000000000..26f705a20 --- /dev/null +++ b/fpga/rvvidaemon/Makefile @@ -0,0 +1,10 @@ +all: rvvidaemon + +rvvidaemon: rvvidaemon.o + gcc $^ /opt/riscv/ImperasDV-OpenHW/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so -o rvvidaemon + +%.o:%.c + gcc -I/opt/riscv/ImperasDV-OpenHW/ImpProprietary/include/host -I/opt/riscv/ImperasDV-OpenHW/ImpPublic/include/host/rvvi/ -c $^ -o $@ + +clean: + rm *.o rvvidaemon diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c new file mode 100644 index 000000000..1e9d17f66 --- /dev/null +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -0,0 +1,500 @@ +/////////////////////////////////////////// +// rvvi daemon +// +// Written: Rose Thomposn ross1728@gmail.com +// Created: 31 May 2024 +// Modified: 31 May 2024 +// +// Purpose: Converts raw socket into rvvi interface to connect into ImperasDV +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rvviApi.h" // *** bug fix me when this file gets included into the correct directory. +#include "idv/idv.h" + + +#define DEST_MAC0 0x43 +#define DEST_MAC1 0x68 +#define DEST_MAC2 0x11 +#define DEST_MAC3 0x11 +#define DEST_MAC4 0x02 +#define DEST_MAC5 0x45 + +#define SRC_MAC0 0x54 +#define SRC_MAC1 0x16 +#define SRC_MAC2 0x00 +#define SRC_MAC3 0x00 +#define SRC_MAC4 0x54 +#define SRC_MAC5 0x8F + +#define BUF_SIZ 1024 + +//#define ETHER_TYPE 0x0801 // The type defined in packetizer.sv +#define ETHER_TYPE 0x5c00 // The type defined in packetizer.sv +//#define ETHER_TYPE 0x0000 // The type defined in packetizer.sv +#define DEFAULT_IF "eno1" + +struct sockaddr_ll socket_address; +uint8_t sendbuf[BUF_SIZ]; +struct ether_header *sendeh = (struct ether_header *) sendbuf; +int tx_len = 0; +int sockfd; + +typedef struct { + uint64_t PC; + uint32_t insn; + uint64_t Mcycle; + uint64_t Minstret; + uint8_t Trap : 1; + uint8_t PrivilegeMode : 2; + uint8_t GPREn : 1; + uint8_t FPREn : 1; + uint16_t CSRCount : 12; + uint8_t GPRReg : 5; + uint64_t GPRValue; + uint8_t FPRReg : 5; + uint64_t FPRValue; + uint8_t CSRWen[3]; + uint16_t CSRReg[3]; + uint64_t CSRValue[3]; + +} RequiredRVVI_t; // total size is 241 bits or 30.125 bytes + +typedef struct { + uint8_t RegAddress : 5; + uint64_t RegValue; +} Reg_t; + +void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData); +void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length); +void PrintInstructionData(RequiredRVVI_t *InstructionData); +int ProcessRvviAll(RequiredRVVI_t *InstructionData); +void set_gpr(int hart, int reg, uint64_t value); +void set_fpr(int hart, int reg, uint64_t value); +int state_compare(int hart, uint64_t Minstret); + +int main(int argc, char **argv){ + + if(argc != 2){ + printf("Wrong number of arguments.\n"); + printf("rvvidaemon \n"); + return -1; + } + + uint8_t buf[BUF_SIZ]; + int sockopt; + struct ifreq ifopts; /* set promiscuous mode */ + struct ether_header *eh = (struct ether_header *) buf; + ssize_t headerbytes, numbytes, payloadbytes; + + /* Open RAW socket to receive frames */ + if ((sockfd = socket(AF_PACKET, SOCK_RAW, htons(ETHER_TYPE))) == -1) { + perror("socket"); + } + printf("Here 0\n"); + + /* Set interface to promiscuous mode - do we need to do this every time? */ + strncpy(ifopts.ifr_name, argv[1], IFNAMSIZ-1); + ioctl(sockfd, SIOCGIFFLAGS, &ifopts); + printf("Here 1\n"); + ifopts.ifr_flags |= IFF_PROMISC; + ioctl(sockfd, SIOCSIFFLAGS, &ifopts); + printf("Here 2\n"); + if (ioctl(sockfd, SIOCGIFINDEX, &ifopts) < 0) + perror("SIOCGIFINDEX"); + + /* Allow the socket to be reused - incase connection is closed prematurely */ + if (setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &sockopt, sizeof sockopt) == -1) { + perror("setsockopt"); + close(sockfd); + exit(EXIT_FAILURE); + } + printf("Here 3\n"); + + /* Bind to device */ + if (setsockopt(sockfd, SOL_SOCKET, SO_BINDTODEVICE, argv[1], IFNAMSIZ-1) == -1) { + perror("SO_BINDTODEVICE"); + close(sockfd); + exit(EXIT_FAILURE); + } + printf("Here 4\n"); + + if(!rvviVersionCheck(RVVI_API_VERSION)){ + printf("Bad RVVI_API_VERSION\n"); + } + + /* Construct the Ethernet header */ + memset(sendbuf, 0, BUF_SIZ); + sendbuf[0] = DEST_MAC0; + sendbuf[1] = DEST_MAC1; + sendbuf[2] = DEST_MAC2; + sendbuf[3] = DEST_MAC3; + sendbuf[4] = DEST_MAC4; + sendbuf[5] = DEST_MAC5; + sendbuf[6] = SRC_MAC0; + sendbuf[7] = SRC_MAC1; + sendbuf[8] = SRC_MAC2; + sendbuf[9] = SRC_MAC3; + sendbuf[10] = SRC_MAC4; + sendbuf[11] = SRC_MAC5; + + sendeh->ether_type = htons(ETHER_TYPE); + tx_len += sizeof(struct ether_header); + /* Packet data */ + sendbuf[tx_len++] = 't'; + sendbuf[tx_len++] = 'r'; + sendbuf[tx_len++] = 'i'; + sendbuf[tx_len++] = 'g'; + sendbuf[tx_len++] = 'i'; + sendbuf[tx_len++] = 'n'; + + rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org"); + rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,"riscv"); + rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"); + rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56); + rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6); + + /* Index of the network device */ + socket_address.sll_ifindex = ifopts.ifr_ifindex; + /* Address length*/ + socket_address.sll_halen = ETH_ALEN; + /* Destination MAC */ + socket_address.sll_addr[0] = DEST_MAC0; + socket_address.sll_addr[1] = DEST_MAC1; + socket_address.sll_addr[2] = DEST_MAC2; + socket_address.sll_addr[3] = DEST_MAC3; + socket_address.sll_addr[4] = DEST_MAC4; + socket_address.sll_addr[5] = DEST_MAC5; + + int i; + printf("buffer: "); + for(i=0;iether_dhost[0] == DEST_MAC0 && + eh->ether_dhost[1] == DEST_MAC1 && + eh->ether_dhost[2] == DEST_MAC2 && + eh->ether_dhost[3] == DEST_MAC3 && + eh->ether_dhost[4] == DEST_MAC4 && + eh->ether_dhost[5] == DEST_MAC5) { + //printf("Correct destination MAC address\n"); + uint64_t PC; + uint32_t insn; + RequiredRVVI_t InstructionData; + DecodeRVVI(buf + headerbytes, payloadbytes, &InstructionData); + // now let's drive IDV + // start simple just drive and compare PC. + PrintInstructionData(&InstructionData); + result = ProcessRvviAll(&InstructionData); + if(result == -1) break; + } + } + + printf("Simulation halted due to mismatch\n"); + + close(sockfd); + + + + return 0; +} + +int ProcessRvviAll(RequiredRVVI_t *InstructionData){ + long int found; + uint64_t time = InstructionData->Mcycle; + uint8_t trap = InstructionData->Trap; + uint64_t order = InstructionData->Minstret; + int result; + + result = 0; + if(InstructionData->GPREn) set_gpr(0, InstructionData->GPRReg, InstructionData->GPRValue); + if(InstructionData->FPREn) set_fpr(0, InstructionData->FPRReg, InstructionData->FPRValue); + + if (trap) { + rvviDutTrap(0, InstructionData->PC, InstructionData->insn); + } else { + rvviDutRetire(0, InstructionData->PC, InstructionData->insn, 0); + } + + if(!trap) result = state_compare(0, InstructionData->Minstret); + // *** set is for nets like interrupts come back to this. + //found = rvviRefNetIndexGet("pc_rdata"); + //rvviRefNetSet(found, InstructionData->PC, time); + return result; + +} + +int state_compare(int hart, uint64_t Minstret){ + uint8_t result = 1; + uint8_t stepOk = 0; + char buf[80]; + rvviDutCycleCountSet(Minstret); + if(rvviRefEventStep(hart) != 0) { + stepOk = 1; + result &= rvviRefPcCompare(hart); + result &= rvviRefInsBinCompare(hart); + result &= rvviRefGprsCompare(hart); + result &= rvviRefFprsCompare(hart); + result &= rvviRefCsrsCompare(hart); + } else { + result = 0; + } + + if (result == 0) { + /* Send packet */ + if (sendto(sockfd, sendbuf, tx_len, 0, (struct sockaddr*)&socket_address, sizeof(struct sockaddr_ll)) < 0){ + printf("Send failed\n"); + }else { + printf("send success!\n"); + } + + sprintf(buf, "MISMATCH @ instruction # %ld\n", Minstret); + idvMsgError(buf); + return -1; + } + +} + +void set_gpr(int hart, int reg, uint64_t value){ + rvviDutGprSet(hart, reg, value); +} + +void set_fpr(int hart, int reg, uint64_t value){ + rvviDutFprSet(hart, reg, value); +} + +void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData){ + // you know this actually easiser in assembly. :( + uint8_t buf2[BUF_SIZ], buf3[BUF_SIZ]; + uint8_t * buf2ptr, *buf3ptr; + buf2ptr = buf2; + buf3ptr = buf3; + //int PayloadSize = sizeof(RequiredRVVI_t) - 1; + int PayloadSize = 30; + int Buf2Size = BUF_SIZ - PayloadSize; + uint64_t Mcycle, Minstret; + uint64_t PC; + uint32_t insn; + // unforunately the struct appoarch does not work?!? + PC = * (uint64_t *) payload; + payload += 8; + insn = * (uint32_t *) payload; + payload += 4; + Mcycle = * (uint64_t *) payload; + payload += 8; + Minstret = * (uint64_t *) payload; + payload += 8; + // the next 4 bytes contain CSRCount (12), FPRWen(1), GPRWen(1), PrivilegeMode(2), Trap(1) + uint32_t RequiredFlags; + RequiredFlags = * (uint32_t *) payload; + uint8_t Trap, PrivilegeMode, GPRWen, FPRWen; + uint16_t CSRCount = 0; + uint8_t GPRReg = 0; + uint64_t GPRData = 0; + uint8_t FPRReg = 0; + uint64_t FPRData = 0; + uint8_t CSRWen[3] = {0, 0, 0}; + uint16_t CSRReg[3]; + uint64_t CSRValue[3]; + int CSRIndex; + + Trap = RequiredFlags & 0x1; + PrivilegeMode = (RequiredFlags >> 1) & 0x3; + GPRWen = (RequiredFlags >> 3) & 0x1; + FPRWen = (RequiredFlags >> 4) & 0x1; + CSRCount = (RequiredFlags >> 5) & 0xFFF; + payload += 2; + + if(GPRWen || FPRWen || (CSRCount != 0)){ + // the first bit of payload is the last bit of CSRCount. + ssize_t newPayloadSize = payloadsize - 30; + BitShiftArray(buf2, payload, 1, newPayloadSize); + int index; + if(GPRWen){ + GPRReg = * (uint8_t *) buf2ptr; + GPRReg = GPRReg & 0x1F; + BitShiftArray(buf3, buf2ptr, 5, newPayloadSize); + GPRData = * (uint64_t *) buf3; + if(FPRWen){ + buf3ptr += 8; + FPRReg = * (uint8_t *) buf3ptr; + BitShiftArray(buf2, buf3ptr, 5, newPayloadSize - 8); + FPRReg = FPRReg & 0x1F; + FPRData = * (uint64_t *) buf2; + } + }else if(FPRWen){ + FPRReg = * (uint8_t *) buf2; + FPRReg = FPRReg & 0x1F; + BitShiftArray(buf3, buf2, 5, newPayloadSize); + FPRData = * (uint64_t *) buf3; + } + if(GPRWen ^ FPRWen){ + payload += 8; + Buf2Size = payloadsize - 38; + BitShiftArray(buf2, payload, 6, Buf2Size); + }else if(GPRWen & FPRWen){ + payload += 17; + Buf2Size = payloadsize - 47; + BitShiftArray(buf2, payload, 3, Buf2Size); + }else{ + Buf2Size = payloadsize - 30; + BitShiftArray(buf2, payload, 1, Buf2Size); + } + buf2ptr = buf2; + for(CSRIndex = 0; CSRIndex < CSRCount; CSRIndex++){ + CSRReg[CSRIndex] = (*(uint16_t *) buf2ptr) & 0xFFF; + Buf2Size -= 1; + BitShiftArray(buf3, buf2ptr + 1, 4, Buf2Size); + CSRValue[CSRIndex] = (*(uint64_t *) buf3); + CSRWen[CSRIndex] = 1; + buf2ptr = buf3; + } + } + InstructionData->PC = PC; + InstructionData->insn = insn; + InstructionData->Mcycle = Mcycle; + InstructionData->Minstret = Minstret; + InstructionData->Trap = Trap; + InstructionData->PrivilegeMode = PrivilegeMode; + InstructionData->GPREn = GPRWen; + InstructionData->FPREn = FPRWen; + InstructionData->CSRCount = CSRCount; + InstructionData->GPRReg = GPRReg; + InstructionData->GPRValue = GPRData; + InstructionData->FPRReg = FPRReg; + InstructionData->FPRValue = FPRData; + for(CSRIndex = 0; CSRIndex < 3; CSRIndex++){ + InstructionData->CSRWen[CSRIndex] = CSRWen[CSRIndex]; + InstructionData->CSRReg[CSRIndex] = CSRReg[CSRIndex]; + InstructionData->CSRValue[CSRIndex] = CSRValue[CSRIndex]; + } +} + +void PrintInstructionData(RequiredRVVI_t *InstructionData){ + int CSRIndex; + printf("PC = %lx, insn = %x, Mcycle = %lx, Minstret = %lx, Trap = %hhx, PrivilegeMode = %hhx", + InstructionData->PC, InstructionData->insn, InstructionData->Mcycle, InstructionData->Minstret, InstructionData->Trap, InstructionData->PrivilegeMode); + if(InstructionData->GPREn){ + printf(", GPR[%d] = %lx", InstructionData->GPRReg, InstructionData->GPRValue); + } + if(InstructionData->FPREn){ + printf(", FPR[%d] = %lx", InstructionData->FPRReg, InstructionData->FPRValue); + } + for(CSRIndex = 0; CSRIndex < 3; CSRIndex++){ + if(InstructionData->CSRWen[CSRIndex]){ + printf(", CSR[%x] = %lx", InstructionData->CSRReg[CSRIndex], InstructionData->CSRValue[CSRIndex]); + } + } + printf("\n"); +} + +void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length){ + // always shift right by ShiftAmount (0 to 7 bit positions). + // *** this implemenation is very inefficient. improve later. + if(ShiftAmount < 0 || ShiftAmount > 7) return; + /* Read the first source byte + Read the second source byte + Right Shift byte 1 by ShiftAmount + Right Rotate byte 2 by ShiftAmount + Mask byte 2 by ~(2^ShiftAmount -1) + OR together the two bytes to form the final next byte + + repeat this for each byte + On the last byte we don't do the last steps + */ + int Index; + for(Index = 0; Index < Length - 1; Index++){ + uint8_t byte1 = src[Index]; + uint8_t byte2 = src[Index+1]; + byte1 = byte1 >> ShiftAmount; + uint8_t byte2rot = (byte2 << (unsigned) (8 - ShiftAmount)) & 0xff; + uint8_t byte1final = byte2rot | byte1; + dst[Index] = byte1final; + } + // fence post + // For last one there is only one source byte + uint8_t byte1 = src[Length-1]; + byte1 = byte1 >> ShiftAmount; + dst[Length-1] = byte1; +} diff --git a/fpga/rvvidaemon/send-copy.c b/fpga/rvvidaemon/send-copy.c new file mode 100644 index 000000000..5d7f85ee8 --- /dev/null +++ b/fpga/rvvidaemon/send-copy.c @@ -0,0 +1,133 @@ + +/* + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEST_MAC0 0x43 +#define DEST_MAC1 0x68 +#define DEST_MAC2 0x11 +#define DEST_MAC3 0x11 +#define DEST_MAC4 0x02 +#define DEST_MAC5 0x45 + +#define SRC_MAC0 0x54 +#define SRC_MAC1 0x16 +#define SRC_MAC2 0x00 +#define SRC_MAC3 0x00 +#define SRC_MAC4 0x54 +#define SRC_MAC5 0x8F + +#define DEFAULT_IF "eth0" +#define BUF_SIZ 1024 +#define ETHER_TYPE 0x5c00 // The type defined in packetizer.sv + +int main(int argc, char *argv[]) +{ + int sockfd; + struct ifreq if_idx; + struct ifreq if_mac; + int tx_len = 0; + char sendbuf[BUF_SIZ]; + struct ether_header *eh = (struct ether_header *) sendbuf; + struct iphdr *iph = (struct iphdr *) (sendbuf + sizeof(struct ether_header)); + struct sockaddr_ll socket_address; + char ifName[IFNAMSIZ]; + + /* Get interface name */ + if (argc > 1) + strcpy(ifName, argv[1]); + else + strcpy(ifName, DEFAULT_IF); + + /* Open RAW socket to send on */ + //if ((sockfd = socket(AF_PACKET, SOCK_RAW, IPPROTO_RAW)) == -1) { + if ((sockfd = socket(AF_PACKET, SOCK_RAW, htons(ETHER_TYPE))) == -1) { + perror("socket"); + } + + /* Get the index of the interface to send on */ + memset(&if_idx, 0, sizeof(struct ifreq)); + strncpy(if_idx.ifr_name, ifName, IFNAMSIZ-1); + if (ioctl(sockfd, SIOCGIFINDEX, &if_idx) < 0) + perror("SIOCGIFINDEX"); + /* Get the MAC address of the interface to send on */ + memset(&if_mac, 0, sizeof(struct ifreq)); + strncpy(if_mac.ifr_name, ifName, IFNAMSIZ-1); + if (ioctl(sockfd, SIOCGIFHWADDR, &if_mac) < 0) + perror("SIOCGIFHWADDR"); + + /* Construct the Ethernet header */ + memset(sendbuf, 0, BUF_SIZ); + /* Ethernet header */ + /* eh->ether_shost[0] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[0]; */ + /* eh->ether_shost[1] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[1]; */ + /* eh->ether_shost[2] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[2]; */ + /* eh->ether_shost[3] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[3]; */ + /* eh->ether_shost[4] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[4]; */ + /* eh->ether_shost[5] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[5]; */ + eh->ether_shost[0] = SRC_MAC0; + eh->ether_shost[1] = SRC_MAC1; + eh->ether_shost[2] = SRC_MAC2; + eh->ether_shost[3] = SRC_MAC3; + eh->ether_shost[4] = SRC_MAC4; + eh->ether_shost[5] = SRC_MAC5; + eh->ether_dhost[0] = DEST_MAC0; + eh->ether_dhost[1] = DEST_MAC1; + eh->ether_dhost[2] = DEST_MAC2; + eh->ether_dhost[3] = DEST_MAC3; + eh->ether_dhost[4] = DEST_MAC4; + eh->ether_dhost[5] = DEST_MAC5; + /* Ethertype field */ + //eh->ether_type = htons(ETH_P_IP); + eh->ether_type = htons(ETHER_TYPE); + tx_len += sizeof(struct ether_header); + + /* Packet data */ + sendbuf[tx_len++] = 0xde; + sendbuf[tx_len++] = 0xad; + sendbuf[tx_len++] = 0xbe; + sendbuf[tx_len++] = 0xef; + + /* Index of the network device */ + socket_address.sll_ifindex = if_idx.ifr_ifindex; + /* Address length*/ + socket_address.sll_halen = ETH_ALEN; + /* Destination MAC */ + socket_address.sll_addr[0] = DEST_MAC0; + socket_address.sll_addr[1] = DEST_MAC1; + socket_address.sll_addr[2] = DEST_MAC2; + socket_address.sll_addr[3] = DEST_MAC3; + socket_address.sll_addr[4] = DEST_MAC4; + socket_address.sll_addr[5] = DEST_MAC5; + + int i; + printf("buffer: "); + for(i=0;i 4'd4; + assign Threshold = Counter >= 4'd4; + assign Mismatch = (mem[Counter] != RvviAxiRdataDelay) & (CurrState == STATE_COMPARE) & RvviAxiRvalidDelay; + assign IlaTriggerOneCycle = CurrState == STATE_TRIGGER; + assign CounterRst = CurrState == STATE_RST; + assign CounterEn = RvviAxiRvalid; + +/* -----\/----- EXCLUDED -----\/----- + always_ff @(posedge clk) begin + if(reset) IlaTrigger <= '0; + else if (IlaTriggerOneCycle) IlaTrigger <= '1; + else if (IlaTriggerAck) IlaTrigger <= '0; + else IlaTrigger <= IlaTrigger; + end + -----/\----- EXCLUDED -----/\----- */ + + // this is a bit hacky, but it works! + logic [3:0] TriggerCount; + logic TriggerReset, TriggerEn; + counter #(4) triggercounter(clk, reset | TriggerReset, TriggerEn, TriggerCount); + assign TriggerReset = TriggerCount == 4'd10; + assign TriggerEn = IlaTriggerOneCycle | (TriggerCount != 4'd0 & TriggerCount < 4'd10); + assign IlaTrigger = TriggerEn; + +endmodule diff --git a/src/wally/csrindextoaddr.sv b/src/wally/csrindextoaddr.sv new file mode 100644 index 000000000..8b2d9e6b7 --- /dev/null +++ b/src/wally/csrindextoaddr.sv @@ -0,0 +1,77 @@ +/////////////////////////////////////////// +// csrindextoaddr.sv +// +// Written: Rose Thompson ross1728@gmail.com +// Created: 24 January 2024 +// Modified: 24 January 2024 +// +// Purpose: Converts the rvvi CSR index into the CSR address +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module csrindextoaddr #(parameter TOTAL_CSRS = 36) ( + input logic [TOTAL_CSRS-1:0] CSRWen, + output logic [11:0] CSRAddr); + + always_comb begin + case(CSRWen) + 36'h0_0000_0000: CSRAddr = 13'h000; + 36'h0_0000_0001: CSRAddr = 13'h300; + 36'h0_0000_0002: CSRAddr = 13'h310; + 36'h0_0000_0004: CSRAddr = 13'h305; + 36'h0_0000_0008: CSRAddr = 13'h341; + 36'h0_0000_0010: CSRAddr = 13'h306; + 36'h0_0000_0020: CSRAddr = 13'h320; + 36'h0_0000_0040: CSRAddr = 13'h302; + 36'h0_0000_0080: CSRAddr = 13'h303; + 36'h0_0000_0100: CSRAddr = 13'h344; + 36'h0_0000_0200: CSRAddr = 13'h304; + 36'h0_0000_0400: CSRAddr = 13'h301; + 36'h0_0000_0800: CSRAddr = 13'h30A; + 36'h0_0000_1000: CSRAddr = 13'hF14; + 36'h0_0000_2000: CSRAddr = 13'h340; + 36'h0_0000_4000: CSRAddr = 13'h342; + 36'h0_0000_8000: CSRAddr = 13'h343; + 36'h0_0001_0000: CSRAddr = 13'hF11; + 36'h0_0002_0000: CSRAddr = 13'hF12; + 36'h0_0004_0000: CSRAddr = 13'hF13; + 36'h0_0008_0000: CSRAddr = 13'hF15; + 36'h0_0010_0000: CSRAddr = 13'h34A; + 36'h0_0020_0000: CSRAddr = 13'h100; + 36'h0_0040_0000: CSRAddr = 13'h104; + 36'h0_0080_0000: CSRAddr = 13'h105; + 36'h0_0100_0000: CSRAddr = 13'h141; + 36'h0_0200_0000: CSRAddr = 13'h106; + 36'h0_0400_0000: CSRAddr = 13'h10A; + 36'h0_0800_0000: CSRAddr = 13'h180; + 36'h0_1000_0000: CSRAddr = 13'h140; + 36'h0_2000_0000: CSRAddr = 13'h143; + 36'h0_4000_0000: CSRAddr = 13'h142; + 36'h0_8000_0000: CSRAddr = 13'h144; + 36'h1_0000_0000: CSRAddr = 13'h14D; + 36'h2_0000_0000: CSRAddr = 13'h001; + 36'h4_0000_0000: CSRAddr = 13'h002; + 36'h8_0000_0000: CSRAddr = 13'h003; + default : CSRAddr = 13'h000; + endcase + end +endmodule + diff --git a/src/wally/priorityaomux.sv b/src/wally/priorityaomux.sv new file mode 100644 index 000000000..d542c946f --- /dev/null +++ b/src/wally/priorityaomux.sv @@ -0,0 +1,46 @@ +/////////////////////////////////////////// +// priorityaomux.sv +// +// Written: Rose Thompson ross1728@gmail.com +// Created: 24 January 2024 +// Modified: 24 January 2024 +// +// Purpose: priority AND-OR MUX. +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module priorityaomux #(parameter ROWS = 8, COLS = 64) ( + input logic [ROWS-1:0] Sel, + input var logic [COLS-1:0] A [ROWS-1:0], + output logic [COLS-1:0] Y, + output logic [ROWS-1:0] SelPriority); + + logic [COLS-1:0] AMasked [ROWS-1:0]; + genvar index; + + priorityonehot #(ROWS) priorityonehot(Sel, SelPriority); + for(index = 0; index < ROWS; index = index + 1) begin + assign AMasked[index] = SelPriority[index] ? A[index] : '0; + end + or_rows #(ROWS, COLS) or_rows(AMasked, Y); + +endmodule + diff --git a/src/wally/regchangedetect.sv b/src/wally/regchangedetect.sv new file mode 100644 index 000000000..8becf867d --- /dev/null +++ b/src/wally/regchangedetect.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// regchangedetect.sv +// +// Written: Rose Thompson ross1728@gmail.com +// Created: 24 January 2024 +// Modified: 24 January 2024 +// +// Purpose: +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module regchangedetect #(parameter XLEN = 64) ( + input clk, reset, + input logic [XLEN-1:0] Value, + output logic Change); + + logic [XLEN-1:0] ValueD; + + flopr #(XLEN) register(clk, reset, Value, ValueD); + assign Change = |(Value ^ ValueD); + +endmodule + diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index d3589a93a..8158a1cfb 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -44,7 +44,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( output logic [2:0] HBURST, output logic [3:0] HPROT, output logic [1:0] HTRANS, - output logic HMASTLOCK + output logic HMASTLOCK, + input logic ExternalStall ); logic StallF, StallD, StallE, StallM, StallW; @@ -274,7 +275,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .StructuralStallD, .LSUStallM, .IFUStallF, - .FPUStallD, + .FPUStallD, .ExternalStall, .DivBusyE, .FDivBusyE, .wfiM, .IntPendingM, // Stall & flush outputs diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 9f5e5ee00..273a7f633 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -32,10 +32,12 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [P.AHBW-1:0] HRDATAEXT, + input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, output logic HSELEXTSDC, + // fpga debug signals + input logic ExternalStall, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, output logic [P.PA_BITS-1:0] HADDR, @@ -75,7 +77,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( wallypipelinedcore #(P) core(.clk, .reset, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, - .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK + .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .ExternalStall ); // instantiate uncore if a bus interface exists @@ -90,4 +92,5 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; end + endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3bf8f1a2e..4885a6121 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,6 +33,8 @@ `include "idv/idv.svh" `endif +// *** bug replace with config? +`define RVVI_SYNTH_SUPPORTED 1 import cvw::*; @@ -114,6 +116,7 @@ module testbench; logic SelectTest; logic TestComplete; logic PrevPCZero; + logic RVVIStall; initial begin // look for arguments passed to simulation, or use defaults @@ -589,7 +592,8 @@ module testbench; assign SDCIntr = 1'b0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall), + .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); @@ -599,6 +603,140 @@ module testbench; clk = 1'b1; # 5; clk = 1'b0; # 5; end + if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth + localparam MAX_CSRS = 3; + logic valid; + logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; + + localparam TOTAL_CSRS = 36; + + // pipeline controlls + logic StallE, StallM, StallW, FlushE, FlushM, FlushW; + // required + logic [P.XLEN-1:0] PCM; + logic InstrValidM; + logic [31:0] InstrRawD; + logic [63:0] Mcycle, Minstret; + logic TrapM; + logic [1:0] PrivilegeModeW; + // registers gpr and fpr + logic GPRWen, FPRWen; + logic [4:0] GPRAddr, FPRAddr; + logic [P.XLEN-1:0] GPRValue, FPRValue; + logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0]; + + assign StallE = dut.core.StallE; + assign StallM = dut.core.StallM; + assign StallW = dut.core.StallW; + assign FlushE = dut.core.FlushE; + assign FlushM = dut.core.FlushM; + assign FlushW = dut.core.FlushW; + assign InstrValidM = dut.core.ieu.InstrValidM; + assign InstrRawD = dut.core.ifu.InstrRawD; + assign PCM = dut.core.ifu.PCM; + assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; + assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + assign TrapM = dut.core.TrapM; + assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW; + assign GPRAddr = dut.core.ieu.dp.regf.a3; + assign GPRWen = dut.core.ieu.dp.regf.we3; + assign GPRValue = dut.core.ieu.dp.regf.wd3; + assign FPRAddr = dut.core.fpu.fpu.fregfile.a4; + assign FPRWen = dut.core.fpu.fpu.fregfile.we4; + assign FPRValue = dut.core.fpu.fpu.fregfile.wd4; + + assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 + assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 + assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 + assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 + assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 + assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 + assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 + assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 + assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 + assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 + assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 + assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A + assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 + assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 + assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 + assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 + assign CSRArray[16] = 0; // 12'hF11 + assign CSRArray[17] = 0; // 12'hF12 + assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 + assign CSRArray[19] = 0; // 12'hF15 + assign CSRArray[20] = 0; // 12'h34A + // supervisor CSRs + assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 + assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 + assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 + assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 + assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 + assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A + assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 + assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 + assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 + assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 + assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 + assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D + // user CSRs + assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 + assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 + assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 + + rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, + .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray, + .valid, .rvvi); + + // axi 4 write data channel + logic [31:0] RvviAxiWdata; + logic [3:0] RvviAxiWstrb; + logic RvviAxiWlast; + logic RvviAxiWvalid; + logic RvviAxiWready; + + logic [3:0] mii_txd; + logic mii_tx_en, mii_tx_er; + + logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; + logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; + + packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, + .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); + + eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), + .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), + .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), + .rx_axis_tlast(), .rx_axis_tuser(), + + .mii_rx_clk(clk), + .mii_rxd('0), + .mii_rx_dv('0), + .mii_rx_er('0), + .mii_tx_clk(clk), + .mii_txd, + .mii_tx_en, + .mii_tx_er, + + // status + .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame, + .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, + .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) + ); + + logic MiiTxEnDelay; + logic EthernetTXCounterEn; + logic [31:0] EthernetTXCount; + flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay); + assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay; + counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount); + + end else begin + assign RVVIStall = '0; + end + + /* // Print key info each cycle for debugging always @(posedge clk) begin diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 2794240be..13092098a 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -60,7 +60,7 @@ module wallywrapper import cvw::*;( logic HREADY; logic HSELEXT; logic HSELEXTSDC; - + logic ExternalStall; // instantiate device to be tested assign GPIOIN = 0; @@ -70,8 +70,9 @@ module wallywrapper import cvw::*;( assign HRESPEXT = 0; assign HRDATAEXT = 0; + assign ExternalStall = '0; - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr);