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Update Coremark makefile

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This commit is contained in:
David Harris 2023-05-16 13:46:20 -07:00
parent 7b0d1a7883
commit 02c61a0d25
1 changed files with 4 additions and 4 deletions
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8
benchmarks/coremark/Makefile
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@ -4,14 +4,14 @@
PORT_DIR = $(CURDIR)/riscv64-baremetal
cmbase=../../addins/coremark
work_dir= ../../benchmarks/coremark/work
work_dir= ../benchmarks/coremark/work
XLEN ?=64
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
ARCH := rv$(XLEN)im
ARCH := rv$(XLEN)gc
PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
@ -23,7 +23,7 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
run:
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
cd ../benchmarks/coremark/
# cd ../benchmarks/coremark/
# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
python3 coremark-postprocess.py
@ -33,7 +33,7 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
extractFunctionRadix.sh $<.elf.objdump
$(work_dir)/coremark.bare.riscv: $(sources) Makefile
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)"
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)"
mkdir -p $(work_dir)
mv $(cmbase)/coremark.bare.riscv $(work_dir)