remerge changes

sim/imperas.ic

@@ -1,20 +1,23 @@
-#--showoverrides
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/mstatus_FS=1
 
 # Enable the Imperas instruction coverage
--extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
--override  refRoot/cpu/cv/cover=basic
--override  refRoot/cpu/cv/extensions=RV32I
+#-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
+#-override  refRoot/cpu/cv/cover=basic
+#-override  refRoot/cpu/cv/extensions=RV32I
 
 # Add Imperas simulator application instruction tracing
 --trace
 --tracechange
 --traceshowicount
 --tracemode
+--tracemem ASX
 --monitornetschange
 
+# Exceptions and pagetables debug
+--override cpu/debugflags=6
+
 # Turn on verbose output for Imperas simulator
 --verbose
 
@@ -24,3 +27,10 @@
 # Store simulator output to logfile
 --output imperas.log
 
+--override cpu/PMP_registers=0
+#--showoverrides
+#--mpdconsole
+
+# ignore settings of bits DAU for non leaf page table walks
+--override cpu/ignore_non_leaf_DAU=1
+

sim/wally-imperas.do

@@ -46,10 +46,12 @@ vsim workopt +nowarn3829  -fatal 7 \
      +testDir=$env(TESTDIR) $env(OTHERFLAGS)
 view wave
 #-- display input and output signals as hexidecimal values
-add log -recursive /*
-do wave.do
+# add log -recursive /*
+# do wave.do
 
 run -all
 
 noview ../testbench/testbench_imperas.sv
 view wave
+
+quit -f

testbench/testbench_imperas.sv

@@ -145,6 +145,7 @@ module testbench;
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,         "riscv.ovpworld.org"));
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,           "riscv"));
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,        "RV64GC"));
+      void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39));
       if (!rvviRefInit(elffilename)) begin
         msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
       end