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Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR

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James E. Stine 2021-09-03 10:26:38 -05:00
parent f1a39b467d
commit 02a1fda650
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wally-pipelined/src/mmu/hptw.sv
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@ -146,6 +146,7 @@ module hptw
if (`XLEN == 32) begin if (`XLEN == 32) begin
assign InitialWalkerState = L1_ADR; assign InitialWalkerState = L1_ADR;
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
// *** Possible bug - should be L1_ADR?
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
end else begin end else begin
logic GigapageMisaligned, TerapageMisaligned; logic GigapageMisaligned, TerapageMisaligned;