From d50a65720db4c88c8f96f56a41bddaea63ae2790 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 30 Dec 2021 09:18:16 -0600 Subject: [PATCH 1/3] More name cleanup in caches. --- wally-pipelined/src/cache/cacheway.sv | 96 +++++------ wally-pipelined/src/cache/dcache.sv | 12 +- wally-pipelined/src/cache/icache.sv | 230 ++++++++++++------------- wally-pipelined/src/cache/icachefsm.sv | 22 +-- wally-pipelined/src/ifu/ifu.sv | 8 +- 5 files changed, 179 insertions(+), 189 deletions(-) diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv index 6d620047d..b1ad1dfd5 100644 --- a/wally-pipelined/src/cache/cacheway.sv +++ b/wally-pipelined/src/cache/cacheway.sv @@ -26,52 +26,52 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, - parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) + parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (input logic clk, - input logic reset, + input logic reset, input logic [$clog2(NUMLINES)-1:0] RAdr, - input logic [`PA_BITS-1:0] PAdr, - input logic WriteEnable, - input logic VDWriteEnable, + input logic [`PA_BITS-1:0] PAdr, + input logic WriteEnable, + input logic VDWriteEnable, input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, - input logic TagWriteEnable, - input logic [BLOCKLEN-1:0] WriteData, - input logic SetValid, - input logic ClearValid, - input logic SetDirty, - input logic ClearDirty, - input logic SelEvict, - input logic VictimWay, - input logic InvalidateAll, - input logic SelFlush, - input logic FlushWay, + input logic TagWriteEnable, + input logic [BLOCKLEN-1:0] WriteData, + input logic SetValid, + input logic ClearValid, + input logic SetDirty, + input logic ClearDirty, + input logic SelEvict, + input logic VictimWay, + input logic InvalidateAll, + input logic SelFlush, + input logic FlushWay, - output logic [BLOCKLEN-1:0] ReadDataBlockWayMasked, - output logic WayHit, - output logic VictimDirtyWay, - output logic [TAGLEN-1:0] VictimTagWay + output logic [BLOCKLEN-1:0] ReadDataLineWayMasked, + output logic WayHit, + output logic VictimDirtyWay, + output logic [TAGLEN-1:0] VictimTagWay ); - logic [NUMLINES-1:0] ValidBits; - logic [NUMLINES-1:0] DirtyBits; - logic [BLOCKLEN-1:0] ReadDataBlockWay; - logic [TAGLEN-1:0] ReadTag; - logic Valid; - logic Dirty; - logic SelectedWay; - logic [TAGLEN-1:0] VicDirtyWay; - logic [TAGLEN-1:0] FlushThisWay; + logic [NUMLINES-1:0] ValidBits; + logic [NUMLINES-1:0] DirtyBits; + logic [BLOCKLEN-1:0] ReadDataBlockWay; + logic [TAGLEN-1:0] ReadTag; + logic Valid; + logic Dirty; + logic SelectedWay; + logic [TAGLEN-1:0] VicDirtyWay; + logic [TAGLEN-1:0] FlushThisWay; - logic [$clog2(NUMLINES)-1:0] RAdrD; - logic SetValidD, ClearValidD; - logic SetDirtyD, ClearDirtyD; - logic WriteEnableD, VDWriteEnableD; + logic [$clog2(NUMLINES)-1:0] RAdrD; + logic SetValidD, ClearValidD; + logic SetDirtyD, ClearDirtyD; + logic WriteEnableD, VDWriteEnableD; - genvar words; + genvar words; generate for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word @@ -92,25 +92,25 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign SelectedWay = SelFlush ? FlushWay : - SelEvict ? VictimWay : WayHit; - assign ReadDataBlockWayMasked = SelectedWay ? ReadDataBlockWay : '0; // first part of AO mux. + SelEvict ? VictimWay : WayHit; + assign ReadDataLineWayMasked = SelectedWay ? ReadDataBlockWay : '0; // first part of AO mux. assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid : - VictimWay & Dirty & Valid; + VictimWay & Dirty & Valid; assign VicDirtyWay = VictimWay ? ReadTag : '0; assign FlushThisWay = FlushWay ? ReadTag : '0; assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay; - + always_ff @(posedge clk) begin if (reset) - ValidBits <= {NUMLINES{1'b0}}; + ValidBits <= {NUMLINES{1'b0}}; else if (InvalidateAll) - ValidBits <= {NUMLINES{1'b0}}; + ValidBits <= {NUMLINES{1'b0}}; else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1; else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0; - end + end always_ff @(posedge clk) begin RAdrD <= RAdr; @@ -120,21 +120,21 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, VDWriteEnableD <= VDWriteEnable; end - + assign Valid = ValidBits[RAdrD]; generate if(DIRTY_BITS) begin always_ff @(posedge clk) begin - if (reset) - DirtyBits <= {NUMLINES{1'b0}}; - else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1; - else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0; + if (reset) + DirtyBits <= {NUMLINES{1'b0}}; + else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1; + else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0; end always_ff @(posedge clk) begin - SetDirtyD <= SetDirty; - ClearDirtyD <= ClearDirty; + SetDirtyD <= SetDirty; + ClearDirtyD <= ClearDirty; end assign Dirty = DirtyBits[RAdrD]; diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index bf8980daf..e2d25477c 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -79,10 +79,10 @@ module dcache logic [BLOCKLEN-1:0] SRAMWriteData; logic SetValid, ClearValid; logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; - logic [BLOCKLEN-1:0] ReadDataBlockM; + logic [BLOCKLEN-1:0] ReadDataLineM; logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SRAMWordWriteEnableM; @@ -137,7 +137,7 @@ module dcache .WriteData(SRAMWriteData), .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .VictimWay, .FlushWay, .SelFlush, - .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), + .ReadDataLineWayMasked, .WayHit, .VictimDirtyWay, .VictimTagWay, .InvalidateAll(1'b0)); @@ -159,10 +159,10 @@ module dcache assign VictimDirty = | VictimDirtyWay; - // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. + // ReadDataLineWayMaskedM is a 2d array of cache block len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMaskedM), .y(ReadDataBlockM)); + or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); @@ -172,7 +172,7 @@ module dcache genvar index; generate for (index = 0; index < WORDSPERLINE; index++) begin - assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)]; + assign ReadDataBlockSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 874ed7f11..5e6f22576 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -28,94 +28,94 @@ module icache ( // Basic pipeline stuff - input logic clk, reset, - input logic StallF, - input logic [`PA_BITS-1:0] PCNextF, - input logic [`PA_BITS-1:0] PCPF, - input logic [`XLEN-1:0] PCF, + input logic clk, reset, + input logic CPUBusy, + input logic [`PA_BITS-1:0] PCNextF, + input logic [`PA_BITS-1:0] PCPF, + input logic [`XLEN-1:0] PCF, - input logic ExceptionM, PendingInterruptM, - + input logic ExceptionM, PendingInterruptM, + // Data read in from the ebu unit - (* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF, - (* mark_debug = "true" *) input logic InstrAckF, + (* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF, + (* mark_debug = "true" *) input logic InstrAckF, // Read requested from the ebu unit (* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF, - (* mark_debug = "true" *) output logic InstrReadF, + (* mark_debug = "true" *) output logic InstrReadF, // High if the instruction currently in the fetch stage is compressed - output logic CompressedF, + output logic CompressedF, // High if the icache is requesting a stall - output logic ICacheStallF, - input logic ITLBMissF, - input logic ITLBWriteF, - input logic InvalidateICacheM, - + output logic ICacheStallF, + input logic CacheableF, + input logic ITLBMissF, + input logic ITLBWriteF, + input logic InvalidateICacheM, + // The raw (not decompressed) instruction that was requested // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros - (* mark_debug = "true" *) output logic [31:0] FinalInstrRawF + (* mark_debug = "true" *) output logic [31:0] FinalInstrRawF ); // Configuration parameters - localparam integer BLOCKLEN = `ICACHE_BLOCKLENINBITS; - localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_BLOCKLENINBITS; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer BLOCKLEN = `ICACHE_BLOCKLENINBITS; + localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_BLOCKLENINBITS; + localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; localparam WORDSPERLINE = BLOCKLEN/`XLEN; localparam LOGWPL = $clog2(WORDSPERLINE); localparam FetchCountThreshold = WORDSPERLINE - 1; - localparam integer PA_WIDTH = `PA_BITS - 2; - localparam integer NUMWAYS = `ICACHE_NUMWAYS; + localparam integer PA_WIDTH = `PA_BITS - 2; + localparam integer NUMWAYS = `ICACHE_NUMWAYS; // Input signals to cache memory - logic ICacheMemWriteEnable; - logic [BLOCKLEN-1:0] ICacheMemWriteData; - logic [`PA_BITS-1:0] PCTagF; + logic ICacheMemWriteEnable; + logic [BLOCKLEN-1:0] ICacheMemWriteData; + logic [`PA_BITS-1:0] PCTagF; // Output signals from cache memory - logic [31:0] ICacheMemReadData; - logic ICacheReadEn; - logic [BLOCKLEN-1:0] ReadLineF; + logic [31:0] ICacheMemReadData; + logic ICacheReadEn; + logic [BLOCKLEN-1:0] ReadLineF; - logic [15:0] SpillDataBlock0; - logic spill; - logic spillSave; + logic [15:0] SpillDataBlock0; + logic spill; + logic spillSave; - logic FetchCountFlag; - logic CntEn; + logic FetchCountFlag; + logic CntEn; - logic [1:1] SelAdr_q; + logic [1:1] SelAdr_q; - logic [LOGWPL-1:0] FetchCount, NextFetchCount; - - logic [`PA_BITS-1:0] PCPSpillF; + logic [LOGWPL-1:0] FetchCount, NextFetchCount; + + logic [`PA_BITS-1:0] PCPSpillF; - logic CntReset; - logic [1:0] SelAdr; - logic [INDEXLEN-1:0] RAdr; - logic [NUMWAYS-1:0] VictimWay; - logic LRUWriteEn; - logic [NUMWAYS-1:0] WayHit; - logic hit; + logic CntReset; + logic [1:0] SelAdr; + logic [INDEXLEN-1:0] RAdr; + logic [NUMWAYS-1:0] VictimWay; + logic LRUWriteEn; + logic [NUMWAYS-1:0] WayHit; + logic hit; - logic [BLOCKLEN-1:0] ReadDataBlockWayMasked [NUMWAYS-1:0]; + logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; - logic CacheableF; - logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF; - logic [OFFSETLEN-1:0] BasePAdrOffsetF; + logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF; + logic [OFFSETLEN-1:0] BasePAdrOffsetF; - logic [NUMWAYS-1:0] SRAMWayWriteEnable; + logic [NUMWAYS-1:0] SRAMWayWriteEnable; // on spill we want to get the first 2 bytes of the next cache block. @@ -125,39 +125,38 @@ module icache mux3 #(INDEXLEN) AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .s(SelAdr), - .y(RAdr)); + .d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .s(SelAdr), + .y(RAdr)); - cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0)) MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, - .PAdr(PCTagF), - .WriteEnable(SRAMWayWriteEnable), - .VDWriteEnable(1'b0), - .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}), - .TagWriteEnable(SRAMWayWriteEnable), - .WriteData(ICacheMemWriteData), - .SetValid(ICacheMemWriteEnable), - .ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0), - .VictimWay, - .FlushWay(1'b0), .SelFlush(1'b0), - .ReadDataBlockWayMasked, .WayHit, - .VictimDirtyWay(), .VictimTagWay(), - .InvalidateAll(InvalidateICacheM)); + .PAdr(PCTagF), + .WriteEnable(SRAMWayWriteEnable), + .VDWriteEnable(1'b0), + .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}), + .TagWriteEnable(SRAMWayWriteEnable), + .WriteData(ICacheMemWriteData), + .SetValid(ICacheMemWriteEnable), + .ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0), + .VictimWay, + .FlushWay(1'b0), .SelFlush(1'b0), + .ReadDataLineWayMasked, .WayHit, + .VictimDirtyWay(), .VictimTagWay(), + .InvalidateAll(InvalidateICacheM)); generate if(NUMWAYS > 1) begin cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(.clk, .reset, - .WayHit, - .VictimWay, - .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .RAdr, - .LRUWriteEn); // *** connect + .WayHit, + .VictimWay, + .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .RAdr, + .LRUWriteEn); end else begin assign VictimWay = 1'b1; // one hot. end @@ -165,10 +164,10 @@ module icache assign hit = | WayHit; - // ReadDataBlockWayMasked is a 2d array of cache block len by number of ways. + // ReadDataLineWayMasked is a 2d array of cache block len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataBlockWayMasked), .y(ReadLineF)); + or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF)); always_comb begin @@ -200,10 +199,10 @@ module icache // can optimize size, for now just make it the size of the data // leaving the cache memory. flopenr #(16) SpillInstrReg(.clk(clk), - .en(spillSave), - .reset(reset), - .d(ICacheMemReadData[15:0]), - .q(SpillDataBlock0)); + .en(spillSave), + .reset(reset), + .d(ICacheMemReadData[15:0]), + .q(SpillDataBlock0)); assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData; @@ -218,10 +217,10 @@ module icache flopenr #(LOGWPL) FetchCountReg(.clk(clk), - .reset(reset | CntReset), - .en(CntEn), - .d(NextFetchCount), - .q(FetchCount)); + .reset(reset | CntReset), + .en(CntEn), + .d(NextFetchCount), + .q(FetchCount)); assign NextFetchCount = FetchCount + 1'b1; @@ -231,10 +230,10 @@ module icache generate for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer flopenr #(`XLEN) sb(.clk(clk), - .reset(reset), - .en(InstrAckF & (i == FetchCount)), - .d(InstrInF), - .q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN])); + .reset(reset), + .en(InstrAckF & (i == FetchCount)), + .d(InstrInF), + .q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN])); end endgenerate @@ -242,25 +241,18 @@ module icache // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // *** read enable may not be necessary. flopenr #(1) SelAdrReg(.clk(clk), - .reset(reset), - .en(ICacheReadEn), - .d(SelAdr[1]), - .q(SelAdr_q[1])); + .reset(reset), + .en(ICacheReadEn), + .d(SelAdr[1]), + .q(SelAdr_q[1])); assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF; // unlike the dcache the victim is never dirty so no eviction is necessary. -/* -----\/----- EXCLUDED -----\/----- - mux2 #(`PA_BITS) BaseAdrMux(.d0(PCTagF), - .d1({VictimTag, PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .s(SelEvict), - .y(BasePAdrF)); - -----/\----- EXCLUDED -----/\----- */ assign BasePAdrF = PCTagF; // if not cacheable the offset bits needs to be sent to the EBU. // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. - assign CacheableF = 1'b1; // *** BUG needs to be an input from MMU. assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : BasePAdrF[OFFSETLEN-1:0]; assign BasePAdrMaskedF = {BasePAdrF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF}; @@ -271,25 +263,25 @@ module icache assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0; icachefsm controller(.clk, - .reset, - .StallF, - .ICacheReadEn, - .ICacheMemWriteEnable, - .ICacheStallF, - .ITLBMissF, - .ITLBWriteF, - .ExceptionM, - .PendingInterruptM, - .InstrAckF, - .InstrReadF, - .hit, - .FetchCountFlag, - .spill, - .spillSave, - .CntEn, - .CntReset, - .SelAdr, - .LRUWriteEn); + .reset, + .CPUBusy, + .ICacheReadEn, + .ICacheMemWriteEnable, + .ICacheStallF, + .ITLBMissF, + .ITLBWriteF, + .ExceptionM, + .PendingInterruptM, + .InstrAckF, + .InstrReadF, + .hit, + .FetchCountFlag, + .spill, + .spillSave, + .CntEn, + .CntReset, + .SelAdr, + .LRUWriteEn); endmodule diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index 867c32c06..4d3ff26a6 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -29,7 +29,7 @@ module icachefsm (// Inputs from pipeline input logic clk, reset, - input logic StallF, + input logic CPUBusy, // inputs from mmu input logic ITLBMissF, @@ -105,10 +105,6 @@ module icachefsm STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the // spill access but does nto consider spill. It also does not do another operation. - STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address? - STATE_TLB_MISS, - STATE_TLB_MISS_DONE, - STATE_CPU_BUSY, STATE_CPU_BUSY_SPILL } statetype; @@ -149,7 +145,7 @@ module icachefsm else if (hit & ~spill) begin ICacheStallF = 1'b0; LRUWriteEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdr = 2'b01; end else begin @@ -169,7 +165,7 @@ module icachefsm SelAdr = 2'b01; NextState = STATE_MISS_SPILL_FETCH_WDV; end else begin - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdr = 2'b01; end else begin @@ -214,7 +210,7 @@ module icachefsm ICacheStallF = 1'b0; LRUWriteEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_SPILL; SelAdr = 2'b10; end else begin @@ -248,7 +244,7 @@ module icachefsm ICacheReadEn = 1'b1; ICacheStallF = 1'b0; LRUWriteEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin SelAdr = 2'b01; NextState = STATE_CPU_BUSY; SelAdr = 2'b01; @@ -293,7 +289,7 @@ module icachefsm SelAdr = 2'b00; ICacheStallF = 1'b0; LRUWriteEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_SPILL; SelAdr = 2'b10; end else begin @@ -326,7 +322,7 @@ module icachefsm SelAdr = 2'b00; ICacheStallF = 1'b0; LRUWriteEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_SPILL; SelAdr = 2'b10; end else begin @@ -335,7 +331,7 @@ module icachefsm end STATE_CPU_BUSY: begin ICacheStallF = 1'b0; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY; SelAdr = 2'b01; end @@ -346,7 +342,7 @@ module icachefsm STATE_CPU_BUSY_SPILL: begin ICacheStallF = 1'b0; ICacheReadEn = 1'b1; - if(StallF) begin + if(CPUBusy) begin NextState = STATE_CPU_BUSY_SPILL; SelAdr = 2'b10; end diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 8bc064a9d..f123ebc07 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -104,6 +104,8 @@ module ifu ( logic [`XLEN+1:0] PCFExt; logic [`XLEN-1:0] PCBPWrongInvalidate; logic BPPredWrongM; + logic CacheableF; + generate @@ -136,7 +138,7 @@ module ifu ( .LoadAccessFaultM(), .StoreAccessFaultM(), .DisableTranslation(1'b0), - .Cacheable(), .Idempotent(), .AtomicAllowed(), + .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(), .clk, .reset, .SATP_REGW, @@ -165,9 +167,9 @@ module ifu ( // 1. ram // controlled by `MEM_IROM // 2. cache // `MEM_ICACHE // 3. wire pass-through - icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF, + icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF, .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, - + .CacheableF, .PCNextF(PCNextFPhys), .PCPF(PCPFmmu), .PCF, From a37c7515bd33ac673a8a1f24178701b8296060cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 30 Dec 2021 10:37:57 -0600 Subject: [PATCH 2/3] Icache now works with any sized cache line a power of 2, greater than or equal to 32. --- wally-pipelined/src/cache/dcache.sv | 2 +- wally-pipelined/src/cache/icache.sv | 39 +++++++++-------------------- 2 files changed, 13 insertions(+), 28 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index e2d25477c..340b0e241 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -178,7 +178,7 @@ module dcache // variable input mux - assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; + assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]]; // Write Path CPU (IEU) side diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 5e6f22576..7b2d0cf37 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -109,7 +109,7 @@ module icache logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; - + logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0]; logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF; logic [OFFSETLEN-1:0] BasePAdrOffsetF; @@ -168,32 +168,17 @@ module icache // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF)); + + genvar index; + generate + for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin + assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)]; + end + assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]}; + endgenerate + + assign ICacheMemReadData = ReadLineSetsF[PCTagF[$clog2(BLOCKLEN / 32) + 1 : 1]]; - - always_comb begin - case (PCTagF[4:1]) - 0: ICacheMemReadData = ReadLineF[31:0]; - 1: ICacheMemReadData = ReadLineF[47:16]; - 2: ICacheMemReadData = ReadLineF[63:32]; - 3: ICacheMemReadData = ReadLineF[79:48]; - - 4: ICacheMemReadData = ReadLineF[95:64]; - 5: ICacheMemReadData = ReadLineF[111:80]; - 6: ICacheMemReadData = ReadLineF[127:96]; - 7: ICacheMemReadData = ReadLineF[143:112]; - - 8: ICacheMemReadData = ReadLineF[159:128]; - 9: ICacheMemReadData = ReadLineF[175:144]; - 10: ICacheMemReadData = ReadLineF[191:160]; - 11: ICacheMemReadData = ReadLineF[207:176]; - - 12: ICacheMemReadData = ReadLineF[223:192]; - 13: ICacheMemReadData = ReadLineF[239:208]; - 14: ICacheMemReadData = ReadLineF[255:224]; - 15: ICacheMemReadData = {16'b0, ReadLineF[255:240]}; - endcase - end - // spills require storing the first cache block so it can merged // with the second // can optimize size, for now just make it the size of the data @@ -208,7 +193,7 @@ module icache // Detect if the instruction is compressed assign CompressedF = FinalInstrRawF[1:0] != 2'b11; - assign spill = PCF[4:1] == 4'b1111 ? 1'b1 : 1'b0; + assign spill = &PCF[$clog2(BLOCKLEN/32)+1:1]; // to compute the fetch address we need to add the bit shifted From 9bcb105aa40ea0493223dd89e2c5672f3d7fbfc5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 30 Dec 2021 11:01:11 -0600 Subject: [PATCH 3/3] Changed names of Icache signals. --- wally-pipelined/regression/wave.do | 8 ++-- wally-pipelined/src/cache/icache.sv | 39 +++++++++---------- wally-pipelined/src/cache/icachefsm.sv | 26 ++++++------- wally-pipelined/src/ebu/ahblite.sv | 22 +++++------ wally-pipelined/src/ifu/ifu.sv | 18 ++++----- .../src/wally/wallypipelinedhart.sv | 16 ++++---- 6 files changed, 63 insertions(+), 66 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 2394f9c36..c4c62ebab 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -175,11 +175,11 @@ add wave -noupdate -group icache -expand -group {fsm out and control} /testbench add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/IfuBusFetch +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF +add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData @@ -187,7 +187,7 @@ add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/IfuBusFetch add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 7b2d0cf37..014edd2de 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -37,11 +37,11 @@ module icache input logic ExceptionM, PendingInterruptM, // Data read in from the ebu unit - (* mark_debug = "true" *) input logic [`XLEN-1:0] InstrInF, - (* mark_debug = "true" *) input logic InstrAckF, + (* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA, + (* mark_debug = "true" *) input logic ICacheBusAck, // Read requested from the ebu unit - (* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF, - (* mark_debug = "true" *) output logic InstrReadF, + (* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr, + (* mark_debug = "true" *) output logic IfuBusFetch, // High if the instruction currently in the fetch stage is compressed output logic CompressedF, // High if the icache is requesting a stall @@ -77,7 +77,7 @@ module icache // Input signals to cache memory logic ICacheMemWriteEnable; logic [BLOCKLEN-1:0] ICacheMemWriteData; - logic [`PA_BITS-1:0] PCTagF; + logic [`PA_BITS-1:0] FinalPCPF; // Output signals from cache memory logic [31:0] ICacheMemReadData; logic ICacheReadEn; @@ -111,7 +111,7 @@ module icache logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0]; - logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF; + logic [`PA_BITS-1:0] BasePAdrMaskedF; logic [OFFSETLEN-1:0] BasePAdrOffsetF; @@ -121,7 +121,7 @@ module icache // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. - assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width. + assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; mux3 #(INDEXLEN) AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), @@ -134,7 +134,7 @@ module icache cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0)) MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, - .PAdr(PCTagF), + .PAdr(FinalPCPF), .WriteEnable(SRAMWayWriteEnable), .VDWriteEnable(1'b0), .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}), @@ -154,7 +154,7 @@ module icache cachereplacementpolicy(.clk, .reset, .WayHit, .VictimWay, - .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .LsuPAdrM(FinalPCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .RAdr, .LRUWriteEn); end else begin @@ -177,7 +177,7 @@ module icache assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]}; endgenerate - assign ICacheMemReadData = ReadLineSetsF[PCTagF[$clog2(BLOCKLEN / 32) + 1 : 1]]; + assign ICacheMemReadData = ReadLineSetsF[FinalPCPF[$clog2(BLOCKLEN / 32) + 1 : 1]]; // spills require storing the first cache block so it can merged // with the second @@ -216,8 +216,8 @@ module icache for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer flopenr #(`XLEN) sb(.clk(clk), .reset(reset), - .en(InstrAckF & (i == FetchCount)), - .d(InstrInF), + .en(ICacheBusAck & (i == FetchCount)), + .d(IfuBusHRDATA), .q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN])); end endgenerate @@ -231,17 +231,14 @@ module icache .d(SelAdr[1]), .q(SelAdr_q[1])); - assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF; - - // unlike the dcache the victim is never dirty so no eviction is necessary. - assign BasePAdrF = PCTagF; + assign FinalPCPF = SelAdr_q[1] ? PCPSpillF : PCPF; // if not cacheable the offset bits needs to be sent to the EBU. // if cacheable the offset bits are discarded. $ FSM will fetch the whole block. - assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : BasePAdrF[OFFSETLEN-1:0]; - assign BasePAdrMaskedF = {BasePAdrF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF}; + assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0]; + assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF}; - assign InstrPAdrF = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF; + assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF; // truncate the offset from PCPF for memory address generation @@ -257,8 +254,8 @@ module icache .ITLBWriteF, .ExceptionM, .PendingInterruptM, - .InstrAckF, - .InstrReadF, + .ICacheBusAck, + .IfuBusFetch, .hit, .FetchCountFlag, .spill, diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index 4d3ff26a6..5de86b37f 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -38,7 +38,7 @@ module icachefsm input logic ExceptionM, PendingInterruptM, // BUS interface - input logic InstrAckF, + input logic ICacheBusAck, // icache internal inputs input logic hit, @@ -54,7 +54,7 @@ module icachefsm output logic ICacheStallF, // Bus interface outputs - output logic InstrReadF, + output logic IfuBusFetch, // icache internal outputs output logic spillSave, @@ -121,7 +121,7 @@ module icachefsm always_comb begin CntReset = 1'b0; PreCntEn = 1'b0; - //InstrReadF = 1'b0; + //IfuBusFetch = 1'b0; ICacheMemWriteEnable = 1'b0; spillSave = 1'b0; SelAdr = 2'b00; @@ -186,9 +186,9 @@ module icachefsm end STATE_HIT_SPILL_MISS_FETCH_WDV: begin SelAdr = 2'b10; - //InstrReadF = 1'b1; + //IfuBusFetch = 1'b1; PreCntEn = 1'b1; - if (FetchCountFlag & InstrAckF) begin + if (FetchCountFlag & ICacheBusAck) begin NextState = STATE_HIT_SPILL_MISS_FETCH_DONE; end else begin NextState = STATE_HIT_SPILL_MISS_FETCH_WDV; @@ -221,9 +221,9 @@ module icachefsm // branch 3 miss no spill STATE_MISS_FETCH_WDV: begin SelAdr = 2'b01; - //InstrReadF = 1'b1; + //IfuBusFetch = 1'b1; PreCntEn = 1'b1; - if (FetchCountFlag & InstrAckF) begin + if (FetchCountFlag & ICacheBusAck) begin NextState = STATE_MISS_FETCH_DONE; end else begin NextState = STATE_MISS_FETCH_WDV; @@ -256,8 +256,8 @@ module icachefsm STATE_MISS_SPILL_FETCH_WDV: begin SelAdr = 2'b01; PreCntEn = 1'b1; - //InstrReadF = 1'b1; - if (FetchCountFlag & InstrAckF) begin + //IfuBusFetch = 1'b1; + if (FetchCountFlag & ICacheBusAck) begin NextState = STATE_MISS_SPILL_FETCH_DONE; end else begin NextState = STATE_MISS_SPILL_FETCH_WDV; @@ -300,8 +300,8 @@ module icachefsm STATE_MISS_SPILL_MISS_FETCH_WDV: begin SelAdr = 2'b10; PreCntEn = 1'b1; - //InstrReadF = 1'b1; - if (FetchCountFlag & InstrAckF) begin + //IfuBusFetch = 1'b1; + if (FetchCountFlag & ICacheBusAck) begin NextState = STATE_MISS_SPILL_MISS_FETCH_DONE; end else begin NextState = STATE_MISS_SPILL_MISS_FETCH_WDV; @@ -358,8 +358,8 @@ module icachefsm endcase end - assign CntEn = PreCntEn & InstrAckF; - assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) || + assign CntEn = PreCntEn & ICacheBusAck; + assign IfuBusFetch = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) || (CurrState == STATE_MISS_FETCH_WDV) || (CurrState == STATE_MISS_SPILL_FETCH_WDV) || (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV); diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 21accf591..3020ee75b 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -40,10 +40,10 @@ module ahblite ( input logic UnsignedLoadM, input logic [1:0] AtomicMaskedM, // Signals from Instruction Cache - input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram - input logic InstrReadF, - output logic [`XLEN-1:0] InstrRData, - output logic InstrAckF, + input logic [`PA_BITS-1:0] ICacheBusAdr, // *** rename these to match block diagram + input logic IfuBusFetch, + output logic [`XLEN-1:0] IfuBusHRDATA, + output logic ICacheBusAck, // Signals from Data Cache input logic [`PA_BITS-1:0] LsuBusAdr, input logic LsuBusRead, @@ -100,23 +100,23 @@ module ahblite ( case (BusState) IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions else if (LsuBusWrite)NextBusState = MEMWRITE; - else if (InstrReadF) NextBusState = INSTRREAD; + else if (IfuBusFetch) NextBusState = INSTRREAD; else NextBusState = IDLE; MEMREAD: if (~HREADY) NextBusState = MEMREAD; - else if (InstrReadF) NextBusState = INSTRREAD; + else if (IfuBusFetch) NextBusState = INSTRREAD; else NextBusState = IDLE; MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; - else if (InstrReadF) NextBusState = INSTRREAD; + else if (IfuBusFetch) NextBusState = INSTRREAD; else NextBusState = IDLE; INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; - else NextBusState = IDLE; // if (InstrReadF still high) + else NextBusState = IDLE; // if (IfuBusFetch still high) default: NextBusState = IDLE; endcase // bus outputs assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); - assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0]; + assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : ICacheBusAdr[31:0]; assign #1 HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize; @@ -136,9 +136,9 @@ module ahblite ( // *** assumes AHBW = XLEN - assign InstrRData = HRDATA; + assign IfuBusHRDATA = HRDATA; assign LsuBusHRDATA = HRDATA; - assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); + assign ICacheBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD); assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE); endmodule diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index f123ebc07..cef67f344 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -31,11 +31,11 @@ module ifu ( input logic StallF, StallD, StallE, StallM, StallW, input logic FlushF, FlushD, FlushE, FlushM, FlushW, // Fetch - input logic [`XLEN-1:0] InstrInF, - input logic InstrAckF, + input logic [`XLEN-1:0] IfuBusHRDATA, + input logic ICacheBusAck, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, - output logic [`PA_BITS-1:0] InstrPAdrF, - output logic InstrReadF, + output logic [`PA_BITS-1:0] ICacheBusAdr, + output logic IfuBusFetch, output logic ICacheStallF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -159,16 +159,16 @@ module ifu ( // *** put memory interface on here, InstrF becomes output - //assign InstrPAdrF = PCF; // *** no MMU - //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later - // assign InstrReadF = 1; // *** & ICacheMissF; add later + //assign ICacheBusAdr = PCF; // *** no MMU + //assign IfuBusFetch = ~StallD; // *** & ICacheMissF; add later + // assign IfuBusFetch = 1; // *** & ICacheMissF; add later // conditional // 1. ram // controlled by `MEM_IROM // 2. cache // `MEM_ICACHE // 3. wire pass-through - icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF, - .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, + icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .IfuBusHRDATA, .ICacheBusAck, + .ICacheBusAdr, .IfuBusFetch, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, .CacheableF, .PCNextF(PCNextFPhys), .PCPF(PCPFmmu), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 815799caf..58cd4b9ae 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -128,10 +128,10 @@ module wallypipelinedhart ( logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] InstrPAdrF; - logic [`XLEN-1:0] InstrRData; - logic InstrReadF; - logic InstrAckF; + logic [`PA_BITS-1:0] ICacheBusAdr; + logic [`XLEN-1:0] IfuBusHRDATA; + logic IfuBusFetch; + logic ICacheBusAck; // AHB LSU interface logic [`PA_BITS-1:0] LsuBusAdr; @@ -164,8 +164,8 @@ module wallypipelinedhart ( .ExceptionM, .PendingInterruptM, // Fetch - .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, - .InstrReadF, .ICacheStallF, + .IfuBusHRDATA, .ICacheBusAck, .PCF, .ICacheBusAdr, + .IfuBusFetch, .ICacheStallF, // Execute .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, @@ -277,8 +277,8 @@ module wallypipelinedhart ( ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .InstrPAdrF, // *** rename these to match block diagram - .InstrReadF, .InstrRData, .InstrAckF, + .ICacheBusAdr, // *** rename these to match block diagram + .IfuBusFetch, .IfuBusHRDATA, .ICacheBusAck, // Signals from Data Cache .LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA, .LsuBusHRDATA,