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Cleaned out unused signals

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This commit is contained in:
David Harris 2021-02-26 09:17:36 -05:00
parent 225102047a
commit 0258901865
11 changed files with 31 additions and 42 deletions
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1
wally-pipelined/src/ebu/ahblite.sv
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@ -38,7 +38,6 @@ module ahblite (
// Signals from Instruction Cache // Signals from Instruction Cache
input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
input logic InstrReadF, input logic InstrReadF,
// input logic ResolveBranchD,
output logic [`XLEN-1:0] InstrRData, output logic [`XLEN-1:0] InstrRData,
// Signals from Data Cache // Signals from Data Cache
input logic [`XLEN-1:0] MemPAdrM, input logic [`XLEN-1:0] MemPAdrM,

2
wally-pipelined/src/ieu/controller.sv
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@ -33,7 +33,6 @@ module controller(
input logic [2:0] Funct3D, input logic [2:0] Funct3D,
input logic [6:0] Funct7D, input logic [6:0] Funct7D,
output logic [2:0] ImmSrcD, output logic [2:0] ImmSrcD,
input logic StallD, FlushD,
input logic IllegalIEUInstrFaultD, input logic IllegalIEUInstrFaultD,
output logic IllegalBaseInstrFaultD, output logic IllegalBaseInstrFaultD,
// Execute stage control signals // Execute stage control signals
@ -48,7 +47,6 @@ module controller(
output logic MulDivE, W64E, output logic MulDivE, W64E,
// Memory stage control signals // Memory stage control signals
input logic StallM, FlushM, input logic StallM, FlushM,
input logic DataMisalignedM,
output logic [1:0] MemRWM, output logic [1:0] MemRWM,
output logic CSRWriteM, PrivilegedM, output logic CSRWriteM, PrivilegedM,
output logic [2:0] Funct3M, output logic [2:0] Funct3M,

4
wally-pipelined/src/ieu/datapath.sv
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@ -28,13 +28,11 @@
module datapath ( module datapath (
input logic clk, reset, input logic clk, reset,
// Decode stage signals // Decode stage signals
input logic StallD, FlushD,
input logic [2:0] ImmSrcD, input logic [2:0] ImmSrcD,
input logic [31:0] InstrD, input logic [31:0] InstrD,
// Execute stage signals // Execute stage signals
input logic StallE, FlushE, input logic StallE, FlushE,
input logic [1:0] ForwardAE, ForwardBE, input logic [1:0] ForwardAE, ForwardBE,
input logic PCSrcE,
input logic [4:0] ALUControlE, input logic [4:0] ALUControlE,
input logic ALUSrcAE, ALUSrcBE, input logic ALUSrcAE, ALUSrcBE,
input logic TargetSrcE, input logic TargetSrcE,
@ -44,8 +42,6 @@ module datapath (
output logic [`XLEN-1:0] SrcAE, SrcBE, output logic [`XLEN-1:0] SrcAE, SrcBE,
// Memory stage signals // Memory stage signals
input logic StallM, FlushM, input logic StallM, FlushM,
input logic [2:0] Funct3M,
input logic RetM, TrapM,
output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] SrcAM,
output logic [`XLEN-1:0] WriteDataM, MemAdrM, output logic [`XLEN-1:0] WriteDataM, MemAdrM,
// Writeback stage signals // Writeback stage signals

5
wally-pipelined/src/ieu/ieu.sv
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@ -49,9 +49,8 @@ module ieu (
input logic [`XLEN-1:0] PCLinkW, input logic [`XLEN-1:0] PCLinkW,
output logic InstrValidW, output logic InstrValidW,
// hazards // hazards
input logic StallF, StallD, StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushE, FlushM, FlushW,
input logic RetM, TrapM,
output logic LoadStallD, MulDivStallD, output logic LoadStallD, MulDivStallD,
output logic PCSrcE, output logic PCSrcE,

4
wally-pipelined/src/ifu/ifu.sv
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@ -36,8 +36,6 @@ module ifu (
output logic [`XLEN-1:0] InstrPAdrF, output logic [`XLEN-1:0] InstrPAdrF,
output logic InstrReadF, output logic InstrReadF,
// Decode // Decode
//output logic InstrStall,
output logic ResolveBranchD,
// Execute // Execute
input logic PCSrcE, input logic PCSrcE,
input logic [`XLEN-1:0] PCTargetE, input logic [`XLEN-1:0] PCTargetE,
@ -60,7 +58,7 @@ module ifu (
logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; logic [`XLEN-1:0] UnalignedPCNextF, PCNextF;
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic StallExceptResolveBranchesF, PrivilegedChangePCM; logic PrivilegedChangePCM;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM; logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
logic CompressedF; logic CompressedF;

2
wally-pipelined/src/muldiv/mul.sv
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@ -61,7 +61,7 @@ module mul (
// flavor of multiplication // flavor of multiplication
assign MULH = (Funct3E == 2'b01); assign MULH = (Funct3E == 2'b01);
assign MULHSU = (Funct3E == 2'b10); assign MULHSU = (Funct3E == 2'b10);
assign MULHU = (Funct3E == 2'b11); // assign MULHU = (Funct3E == 2'b11); // signal unused
// Handle signs // Handle signs
assign PP1 = Pprime; // same for all flavors assign PP1 = Pprime; // same for all flavors

7
wally-pipelined/src/privileged/csrs.sv
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@ -60,15 +60,13 @@ module csrs #(parameter
// Supervisor mode CSRs sometimes supported // Supervisor mode CSRs sometimes supported
generate generate
if (`S_SUPPORTED) begin if (`S_SUPPORTED) begin
logic WriteSTVECM, WriteSEDELEGM, WriteSIDELEGM; logic WriteSTVECM;
logic WriteSSCRATCHM, WriteSEPCM; logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW, SATP_REGW; logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW, SATP_REGW;
assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS); assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS);
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC);
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH); assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH);
assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)); assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC));
assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)); assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE));
@ -85,6 +83,9 @@ module csrs #(parameter
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW); flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
if (`N_SUPPORTED) begin if (`N_SUPPORTED) begin
logic WriteSEDELEGM, WriteSIDELEGM;
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW);
flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW);
end else begin end else begin

20
wally-pipelined/src/uncore/clint.sv
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@ -67,10 +67,10 @@ module clint (
if (`XLEN==64) begin if (`XLEN==64) begin
always @(posedge HCLK) begin always @(posedge HCLK) begin
case(entry) case(entry)
16'h0000: HREADCLINT = {63'b0, MSIP}; 16'h0000: HREADCLINT <= {63'b0, MSIP};
16'h4000: HREADCLINT = MTIMECMP; 16'h4000: HREADCLINT <= MTIMECMP;
16'hBFF8: HREADCLINT = MTIME; 16'hBFF8: HREADCLINT <= MTIME;
default: HREADCLINT = 0; default: HREADCLINT <= 0;
endcase endcase
end end
always_ff @(posedge HCLK or negedge HRESETn) always_ff @(posedge HCLK or negedge HRESETn)
@ -89,12 +89,12 @@ module clint (
end else begin // 32-bit end else begin // 32-bit
always @(posedge HCLK) begin always @(posedge HCLK) begin
case(entry) case(entry)
16'h0000: HREADCLINT = {31'b0, MSIP}; 16'h0000: HREADCLINT <= {31'b0, MSIP};
16'h4000: HREADCLINT = MTIMECMP[31:0]; 16'h4000: HREADCLINT <= MTIMECMP[31:0];
16'h4004: HREADCLINT = MTIMECMP[63:32]; 16'h4004: HREADCLINT <= MTIMECMP[63:32];
16'hBFF8: HREADCLINT = MTIME[31:0]; 16'hBFF8: HREADCLINT <= MTIME[31:0];
16'hBFFC: HREADCLINT = MTIME[63:32]; 16'hBFFC: HREADCLINT <= MTIME[63:32];
default: HREADCLINT = 0; default: HREADCLINT <= 0;
endcase endcase
end end
always_ff @(posedge HCLK or negedge HRESETn) always_ff @(posedge HCLK or negedge HRESETn)

24
wally-pipelined/src/uncore/uart.sv
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@ -57,24 +57,24 @@ module uart (
always @(posedge HCLK) begin always @(posedge HCLK) begin
HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
case (HADDR) case (HADDR)
3'b000: Din = HWDATA[7:0]; 3'b000: Din <= HWDATA[7:0];
3'b001: Din = HWDATA[15:8]; 3'b001: Din <= HWDATA[15:8];
3'b010: Din = HWDATA[23:16]; 3'b010: Din <= HWDATA[23:16];
3'b011: Din = HWDATA[31:24]; 3'b011: Din <= HWDATA[31:24];
3'b100: Din = HWDATA[39:32]; 3'b100: Din <= HWDATA[39:32];
3'b101: Din = HWDATA[47:40]; 3'b101: Din <= HWDATA[47:40];
3'b110: Din = HWDATA[55:48]; 3'b110: Din <= HWDATA[55:48];
3'b111: Din = HWDATA[63:56]; 3'b111: Din <= HWDATA[63:56];
endcase endcase
end end
end else begin // 32-bit end else begin // 32-bit
always @(posedge HCLK) begin always @(posedge HCLK) begin
HREADUART = {Dout, Dout, Dout, Dout}; HREADUART = {Dout, Dout, Dout, Dout};
case (HADDR[1:0]) case (HADDR[1:0])
2'b00: Din = HWDATA[7:0]; 2'b00: Din <= HWDATA[7:0];
2'b01: Din = HWDATA[15:8]; 2'b01: Din <= HWDATA[15:8];
2'b10: Din = HWDATA[23:16]; 2'b10: Din <= HWDATA[23:16];
2'b11: Din = HWDATA[31:24]; 2'b11: Din <= HWDATA[31:24];
endcase endcase
end end
end end

2
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -78,8 +78,6 @@ module wallypipelinedhart (
logic LoadMisalignedFaultM, LoadAccessFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreMisalignedFaultM, StoreAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM; logic [`XLEN-1:0] InstrMisalignedAdrM;
logic [`XLEN-1:0] zero = 0;
logic ResolveBranchD;
logic PCSrcE; logic PCSrcE;
logic CSRWritePendingDEM; logic CSRWritePendingDEM;

2
wally-pipelined/src/wally/wallypipelinedsoc.sv
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@ -56,7 +56,6 @@ module wallypipelinedsoc (
// to instruction memory *** remove later // to instruction memory *** remove later
logic [`XLEN-1:0] PCF; logic [`XLEN-1:0] PCF;
logic [31:0] InstrF;
// Uncore signals // Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
@ -68,6 +67,7 @@ module wallypipelinedsoc (
logic [3:0] HSIZED; logic [3:0] HSIZED;
logic HWRITED; logic HWRITED;
logic [15:0] rd2; // bogus, delete when real multicycle fetch works logic [15:0] rd2; // bogus, delete when real multicycle fetch works
logic [31:0] InstrF;
// instantiate processor and memories // instantiate processor and memories
wallypipelinedhart hart(.*); wallypipelinedhart hart(.*);