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Removed .* from mmu instance inside lsu.sv.
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@ -187,7 +187,9 @@ module lsu
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.DCacheStall(DCacheStall));
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.DCacheStall(DCacheStall));
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.PAdr(MemPAdrMtoDCache),
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(DisableTranslation),
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.PAdr(MemPAdrMtoDCache),
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.VAdr(MemAdrM),
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.VAdr(MemAdrM),
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.Size(Funct3MtoDCache[1:0]),
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.Size(Funct3MtoDCache[1:0]),
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.PTE(PTE),
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.PTE(PTE),
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@ -196,18 +198,16 @@ module lsu
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.TLBFlush(DTLBFlushM),
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.TLBFlush(DTLBFlushM),
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.PhysicalAddress(MemPAdrM),
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.PhysicalAddress(MemPAdrM),
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.TLBMiss(DTLBMissM),
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.TLBMiss(DTLBMissM),
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.TLBPageFault(DTLBPageFaultM),
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.ExecuteAccessF(1'b0),
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//.AtomicAccessM(AtomicMaskedM[1]),
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.AtomicAccessM(1'b0),
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.WriteAccessM(MemRWMtoLRSC[0]),
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.ReadAccessM(MemRWMtoLRSC[1]),
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.DisableTranslation(DisableTranslation),
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.InstrAccessFaultF(),
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.Cacheable(CacheableM),
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.Cacheable(CacheableM),
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.Idempotent(),
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.Idempotent(),
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.AtomicAllowed(),
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.AtomicAllowed(),
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.*); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
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.TLBPageFault(DTLBPageFaultM),
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.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
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.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),
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.WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
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//.AtomicAccessM(AtomicMaskedM[1]),
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); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
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assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
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assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
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