Merge branch 'main' of https://github.com/openhwgroup/cvw

src/wrappers/wallypipelinedcorewrapper.sv

@@ -1,56 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedcorewrapper.sv
-//
-// Written: Kevin Kim kekim@hmc.edu 21 August 2023
-// Modified: 
-//
-// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
-//          not system verilog.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-//`include "BranchPredictorType.vh"
-`include "config.vh"
-
-import cvw::*;
-
-`include "parameter-defs.vh"
-module wallypipelinedcorewrapper (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [P.XLEN-1:0]     HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [P.PA_BITS-1:0]  HADDR,
-   output logic [32-1:0]     HWDATA,
-   output logic [32/8-1:0]   HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
-);
-
-  wallypipelinedcore  #(P) core(.*); 
-
-endmodule

synthDC/Makefile

@@ -119,6 +119,8 @@ ifeq ($(SAIFPOWER), 1)
 endif
 
 
+mkwrapper:
+	python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN)
 mkdirecs:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
@@ -128,7 +130,7 @@ mkdirecs:
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
 
-synth: mkdirecs configs rundc # clean
+synth: mkwrapper mkdirecs configs rundc # clean
 
 rundc:
 ifeq ($(TECH), tsmc28psyn)
@@ -148,3 +150,4 @@ clean:
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
+	rm $(WALLY)/synthDC/wrappers/*

synthDC/scripts/synth.tcl

@@ -29,6 +29,7 @@ eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
 #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
+eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
 
 # Only for FMA class project; comment out when done
 # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
@@ -42,7 +43,7 @@ if { $saifpower == 1 } {
 set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel
-set my_toplevel $::env(DESIGN)
+set my_toplevel $::env(DESIGN)wrapper
 
 # Set number of significant digits
 set report_default_significant_digits 6

synthDC/scripts/wrapperGen.py

@@ -1,3 +1,4 @@
+#!/usr/bin/python3
 """
 wrapperGen.py
 
@@ -7,16 +8,19 @@ script that generates top-level wrappers for verilog modules to synthesize
 """
 
 import argparse
+import glob
 import os
 
 #create argument parser
 parser = argparse.ArgumentParser()
 
-parser.add_argument("fin")
+parser.add_argument("DESIGN")
 
 args=parser.parse_args()
 
-fin = open(args.fin, "r")
+fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0]
+
+fin = open(fin_path, "r")
 
 lines = fin.readlines()
 
@@ -55,9 +59,8 @@ for l in lines:
 # post-processing buffer: add DUT and endmodule lines
 buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
 
-
 # path to wrapper
-wrapperPath = f"{os.getenv('WALLY')}/src/wrappers/{moduleName}wrapper.sv"
+wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
 
 # clear wrappers directory 
 os.system(f"rm {os.getenv('WALLY')}/src/wrappers/*")

synthDC/wrappers/wallypipelinedcorewrapper.sv

@@ -0,0 +1,24 @@
+import cvw::*;
+`include "config.vh"
+`include "parameter-defs.vh"
+module wallypipelinedcorewrapper (
+   input  logic                  clk, reset,
+   // Privileged
+   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
+   input  logic [63:0]           MTIME_CLINT, 
+   // Bus Interface
+   input  logic [P.AHBW-1:0]     HRDATA,
+   input  logic                  HREADY, HRESP,
+   output logic                  HCLK, HRESETn,
+   output logic [P.PA_BITS-1:0]  HADDR,
+   output logic [P.AHBW-1:0]     HWDATA,
+   output logic [P.XLEN/8-1:0]   HWSTRB,
+   output logic                  HWRITE,
+   output logic [2:0]            HSIZE,
+   output logic [2:0]            HBURST,
+   output logic [3:0]            HPROT,
+   output logic [1:0]            HTRANS,
+   output logic                  HMASTLOCK
+);
+	wallypipelinedcore #(P) dut(.*);
+endmodule