diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 74f5162ba..19f96c98d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -265,11 +265,11 @@ module controller import cvw::*; #(parameter cvw_t P) ( 7'b0100111: if (FLSFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported 7'b0101111: if (AFunctD) begin - if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) + if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr - else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011) + else if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00011) ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc - else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) + else if (P.ZAAMO_SUPPORTED & AMOFunctD) ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo end 7'b0110011: if (RFunctD) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c04d0a4a6..65eafe7f7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -138,6 +138,6 @@ module datapath import cvw::*; #(parameter cvw_t P) ( mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); // handle Store Conditional result if atomic extension supported - if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; - else assign SCResultW = '0; + if (P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; + else assign SCResultW = '0; endmodule diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 437797859..cbe567ae3 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -48,7 +48,7 @@ module extend import cvw::*; #(parameter cvw_t P) ( // U-type (lui, auipc) 3'b100: ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset - 3'b101: if (P.A_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0; + 3'b101: if (P.ZALRSC_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0; else ImmExtD = undefined; default: ImmExtD = undefined; // undefined endcase diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index ed2830868..695603758 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -400,7 +400,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); // InstrM is only needed with CSRs or atomic operations - if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin + if (P.ZICSR_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM); end else assign InstrM = '0; diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index e318260ab..1e3419dec 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -49,14 +49,14 @@ module atomic import cvw::*; #(parameter cvw_t P) ( logic MemReadM; // AMO ALU - if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin + if (P.ZAAMO_SUPPORTED) begin amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); end else assign IMAWriteDataM = IHWriteDataM; // LRSC unit - if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin + if (P.ZALRSC_SUPPORTED) begin assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index cbe144cbc..900b63eda 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -392,7 +392,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// - if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic + if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 0872ab1de..c0f13d8ff 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -51,7 +51,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.DCACHE_SUPPORTED == 0 & P.ICACHE_SUPPORTED == 0) | P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED."); assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (P.DCACHE_SUPPORTED | (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally."); + assert (P.DCACHE_SUPPORTED | (P.ZAAMO_SUPPORTED == 0 & P.ZALRSC_SUPPORTED == 0)) else $fatal(1, "Atomic extension (ZAAMO/ZALRSC) requires cache on Wally."); assert (P.IDIV_ON_FPU == 0 | P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 | (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED"); assert ((P.M_SUPPORTED == 0) | (P.ZMMUL_SUPPORTED == 1)) else $fatal(1, "M requires ZMMUL"); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c53e0a842..f3ca4e536 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -145,7 +145,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; - "arch64a_amo": if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) tests = arch64a_amo; + "arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo; "arch64f": if (P.F_SUPPORTED) tests = arch64f; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; @@ -159,7 +159,7 @@ module testbench; "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; "wally64q": if (P.Q_SUPPORTED) tests = wally64q; - "wally64a_lrsc": if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) tests = wally64a_lrsc; + "wally64a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally64a_lrsc; "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "custom": tests = custom; @@ -198,7 +198,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; - "arch32a_amo": if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) tests = arch32a_amo; + "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; "arch32f": if (P.F_SUPPORTED) tests = arch32f; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; @@ -210,7 +210,7 @@ module testbench; "imperas32i": tests = imperas32i; "imperas32f": if (P.F_SUPPORTED) tests = imperas32f; "imperas32m": if (P.M_SUPPORTED) tests = imperas32m; - "wally32a_lrsc": if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; + "wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; "imperas32c": if (P.C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i;