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Remove remnants of InstrReadC

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Thomas Fleming 2021-05-03 17:36:25 -04:00
parent 94d734cca9
commit 00c3b5a033
1 changed files with 2 additions and 2 deletions
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wally-pipelined/src/ebu/ahblite.sv
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@ -129,7 +129,7 @@ module ahblite (
else if (InstrReadF) ProposedNextBusState = INSTRREAD; else if (InstrReadF) ProposedNextBusState = INSTRREAD;
else ProposedNextBusState = IDLE; else ProposedNextBusState = IDLE;
MEMREAD: if (~HREADY) ProposedNextBusState = MEMREAD; MEMREAD: if (~HREADY) ProposedNextBusState = MEMREAD;
else if (InstrReadF) ProposedNextBusState = INSTRREADC; else if (InstrReadF) ProposedNextBusState = INSTRREAD;
else ProposedNextBusState = IDLE; else ProposedNextBusState = IDLE;
MEMWRITE: if (~HREADY) ProposedNextBusState = MEMWRITE; MEMWRITE: if (~HREADY) ProposedNextBusState = MEMWRITE;
else if (InstrReadF) ProposedNextBusState = INSTRREAD; else if (InstrReadF) ProposedNextBusState = INSTRREAD;
@ -141,7 +141,7 @@ module ahblite (
// Determine access type (important for determining whether to fault) // Determine access type (important for determining whether to fault)
assign AtomicAccessM = (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE); assign AtomicAccessM = (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
assign ExecuteAccessF = (ProposedNextBusState == INSTRREAD) || (ProposedNextBusState == INSTRREADC); assign ExecuteAccessF = (ProposedNextBusState == INSTRREAD);
assign WriteAccessM = (ProposedNextBusState == MEMWRITE) || (ProposedNextBusState == ATOMICWRITE); assign WriteAccessM = (ProposedNextBusState == MEMWRITE) || (ProposedNextBusState == ATOMICWRITE);
assign ReadAccessM = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == ATOMICREAD) || assign ReadAccessM = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == ATOMICREAD) ||
(ProposedNextBusState == MMUTRANSLATE); (ProposedNextBusState == MMUTRANSLATE);