From c33230d1c1995c78fcda438ea71618b79c63e1e2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 6 Feb 2023 17:32:28 -0600 Subject: [PATCH] Fixed Bug 66. If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish. --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 78975e38e..c0b7ad933 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -245,7 +245,7 @@ module hptw ( flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) - IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; + IDLE: if (TLBMiss & ~DCacheStallM) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;