Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors

bin/regression-wally

@@ -237,6 +237,10 @@ def addTests(tests, sim):
 
 def search_log_for_text(text, grepfile):
     """Search through the given log file for text, returning True if it is found or False if it is not"""
+    grepwarn = "grep -H Warning: " + grepfile
+    os.system(grepwarn)
+    greperr = "grep -H Error: " + grepfile
+    os.system(greperr)
     grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
 #    print("  search_log_for_text invoking %s" % grepcmd)
     return os.system(grepcmd) == 0

config/shared/config-shared.vh

@@ -129,14 +129,3 @@ localparam CORRSHIFTSZ = NORMSHIFTSZ-2;                             // Drop lead
 /* verilator lint_off STMTDLY */
 /* verilator lint_off ASSIGNDLY */
 /* verilator lint_off PINCONNECTEMPTY */
-
-`ifdef VERILATOR
-    import "DPI-C" function string getenvval(input string env_name);
-    string       RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
-    string       WALLY_DIR = getenvval("WALLY"); 
-`else
-//    import "DPI-C" function string getenv(input string env_name);
-//    string       RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
-    string       RISCV_DIR = "$RISCV"; // "/opt/riscv";
-    string       WALLY_DIR = "$WALLY";
-`endif

sim/vcs/run_vcs

@@ -29,7 +29,6 @@ clean() {
 clean
 #vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
 # lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO]
-# ,noOBSV2G
+vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
-vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
 ./$OUTPUT | tee program.out
 

src/cvw.sv

@@ -293,7 +293,6 @@ typedef struct packed {
   int DURLEN     ;
   int DIVb       ;
   int DIVBLEN    ;
-
 } cvw_t;
 
 endpackage

src/generic/mem/rom1p1r.sv

@@ -26,6 +26,13 @@
 
 // This model actually works correctly with vivado.
 
+`ifdef VERILATOR
+    import "DPI-C" function string getenvval(input string env_name);
+    string       WALLY_DIR = getenvval("WALLY"); 
+`else
+    string       WALLY_DIR = "$WALLY";
+`endif
+
 module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
   (input  logic                  clk,
    input  logic                  ce,
@@ -47,7 +54,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
   end else begin */
 
   initial 
-    if (PRELOAD_ENABLED) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0);
+    if (PRELOAD_ENABLED) begin
+      if (DATA_WIDTH == 64) $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0);  // load boot ROM for FPGA
+      else begin // put something in the ROM so it is not optimized away
+        ROM[0] = 'h00002197;
+      end
+    end
 
   always_ff @ (posedge clk) 
     if(ce) dout <= ROM[addr];

testbench/testbench.sv

@@ -33,6 +33,13 @@
     `include "idv/idv.svh"
 `endif
 
+`ifdef VERILATOR
+    import "DPI-C" function string getenvval(input string env_name);
+    string       RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
+`else
+    string       RISCV_DIR = "$RISCV"; // "/opt/riscv";
+`endif
+
 import cvw::*;
 
 module testbench;