From 6cb554960cbef3ee287700dfb9dd162baa010407 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Apr 2024 16:34:31 -0700 Subject: [PATCH 1/6] Updated README about installation --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 6379f35a8..5fd85ea55 100644 --- a/README.md +++ b/README.md @@ -49,25 +49,25 @@ Add the following lines to your .bashrc or .bash_profile to run the setup script Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. - export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server - export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server - export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa - export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler + export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server + export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server + export QUESTAPATH=.. # Change this for your path to Questa + export SNPSPATH=.. # Change this for your path to Design Compiler If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below. Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while. $ make - $ cd sim - $ ./regression-wally (depends on having Questa installed) + $ regression-wally (depends on having Questa installed) # Toolchain Installation (Sys Admin) This section describes the open source toolchain installation. The -current version of the toolchain has been tested on Ubuntu and Red +current version of the toolchain has been tested on Ubuntu and partly on Red Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended -unless you have a compelling need for RedHat. +unless you have a compelling need for RedHat. However, Ubuntu 22.04LTS +is incompatible with Synopsys Design Compiler. Ubuntu users can install the tools by running From 06e34b7be4fad872649d58b56f2c44da3349dd17 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 27 Apr 2024 06:25:24 -0700 Subject: [PATCH 2/6] Fixed byte enables for synthesis --- src/generic/mem/ram1p1rwbe.sv | 3 ++- src/generic/mem/ram1p1rwe.sv | 7 ++++--- src/generic/mem/ram2p1r1wbe.sv | 19 ++++++++++--------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4da48d760..a0dd5aef4 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// -// 1 port sram. +// ram1p1r2be.sv +// 1 port sram with byte enables // // Written: ross1728@gmail.com // Created: 3 May 2021 diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index ff844ff22..a030d2aab 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// ram1p1rwe.sv // 1 port sram. // // Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com) @@ -49,19 +50,19 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB(0), .Q(dout)); + .BWEB('0), .Q(dout)); end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag // 64 x 44-bit SRAM ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB(0), .Q(dout)); + .BWEB('0), .Q(dout)); end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag // 64 x 22-bit SRAM ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB(0), .Q(dout)); + .BWEB('0), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index d711fce7a..c4cee8b7e 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// ram2p1r1wbe.sv // 2 port sram. // // Written: ross1728@gmail.com May 3, 2021 @@ -55,11 +56,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA(0), .WEBB(~we2), + .WEBA(1'b0), .WEBB(~we2), .AA(ra1), .AB(wa2), - .DA(0), + .DA('0), .DB(wd2), - .BWEBA(0), .BWEBB('1), + .BWEBA('0), .BWEBB('1), .QA(rd1), .QB()); @@ -67,11 +68,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA(0), .WEBB(~we2), + .WEBA(1'b0), .WEBB(~we2), .AA(ra1), .AB(wa2), - .DA(0), + .DA('0), .DB(wd2), - .BWEBA(0), .BWEBB('1), + .BWEBA('0), .BWEBB('1), .QA(rd1), .QB()); @@ -95,12 +96,12 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA(0), .WEBB(~we2), + .WEBA(1'b0), .WEBB(~we2), .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .DA(0), + .DA('0), .DB(SRAMWriteData), - .BWEBA(0), .BWEBB(SRAMBitMask), + .BWEBA('0), .BWEBB(SRAMBitMask), .QA(SRAMReadData), .QB()); From 2b50b30f23140eabc712b6c098003d1ce9d14499 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 27 Apr 2024 07:18:26 -0700 Subject: [PATCH 3/6] Updated extractSummary to read synthesis outputs in new form --- synthDC/extractSummary.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index d6f5933a9..7c3848b9c 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -33,15 +33,19 @@ def synthsintocsv(): for oneSynth in allSynths: descrip = specReg.findall(oneSynth) - width = descrip[2][:4] - config = descrip[2][4:] - if descrip[3][-2:] == 'nm': + if (descrip[3] == "sram"): + base = 4 + else: + base = 3 + width = descrip[base][:4] + config = descrip[base][4:] + if descrip[base+1][-2:] == 'nm': mod = '' else: - mod = descrip[3] + mod = descrip[base+1] descrip = descrip[1:] - tech = descrip[3][:-2] - freq = descrip[4] + tech = descrip[base+1][:-2] + freq = descrip[base+2] metrics = [] for phrase in ['Path Slack', 'Design Area']: bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*' From 12c5879467aeb8bfcf214d30e7aadfde0e6422f7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 27 Apr 2024 17:06:44 -0700 Subject: [PATCH 4/6] Synthesis with derived configs --- config/derivlist.txt | 20 ++++++++++---------- synthDC/Makefile | 4 ++++ synthDC/extractSummary.py | 5 +++++ synthDC/wallySynth.py | 4 +--- 4 files changed, 20 insertions(+), 13 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 86b80310b..da3bae5cb 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -89,29 +89,29 @@ deriv syn_sram_rv64i rv64i syn_sram_rv32e deriv syn_sram_rv64gc rv64gc syn_sram_rv32e # The following syn configurations gradually turn off features -deriv syn_pmp0_rv64gc syn_rv64gc +deriv syn_rv64gc_pmp0 syn_rv64gc PMP_ENTRIES 32'd0 -deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc +deriv syn_sram_rv64gc_pmp0 syn_sram_rv64gc PMP_ENTRIES 32'd0 -deriv syn_noPriv_rv64gc syn_pmp0_rv64gc +deriv syn_rv64gc_noPriv syn_rv64gc_pmp0 ZICSR_SUPPORTED 0 -deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc +deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0 ZICSR_SUPPORTED 0 -deriv syn_noFPU_rv64gc syn_noPriv_rv64gc +deriv syn_rv64gc_noFPU syn_rv64gc_noPriv MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) -deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc +deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) -deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc +deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) -deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc +deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) -deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc +deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv MISA (32'h00000104 | 1 << 18 | 1 << 20) -deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc +deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv MISA (32'h00000104 | 1 << 18 | 1 << 20) # Divider variants to check logical correctness diff --git a/synthDC/Makefile b/synthDC/Makefile index 068df0c70..513d54dba 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -44,7 +44,11 @@ configs: $(CONFIG) $(CONFIG): @echo $(CONFIG) cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) +ifeq ($(MOD), orig) cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true +else + cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)_$(MOD)/config.vh $(CONFIGDIR) | true +endif ifeq ($(SAIFPOWER), 1) cp -f ../sim/power.saif . diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 7c3848b9c..150f20efb 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -33,6 +33,9 @@ def synthsintocsv(): for oneSynth in allSynths: descrip = specReg.findall(oneSynth) + print("From " + oneSynth + " Find ") + for d in descrip: + print(d) if (descrip[3] == "sram"): base = 4 else: @@ -46,10 +49,12 @@ def synthsintocsv(): descrip = descrip[1:] tech = descrip[base+1][:-2] freq = descrip[base+2] +# print(width, config, mod, tech, freq) metrics = [] for phrase in ['Path Slack', 'Design Area']: bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*' bashCommand = bashCommand.format(phrase) + print(bashCommand) try: output = subprocess.check_output(['bash','-c', bashCommand]) nums = metricReg.findall(str(output)) diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index a4d9fc2f5..a5e8b5d6b 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -11,8 +11,6 @@ def runSynth(config, mod, tech, freq, maxopt, usesram): prefix = "syn_sram_" else: prefix = "syn_" - if (mod != "orig"): - prefix = prefix+mod+"_" cfg = prefix + config command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(cfg, mod, tech, freq, maxopt, usesram) pool.map(mask, [command]) @@ -63,7 +61,7 @@ if __name__ == '__main__': defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: + for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'pmp0']: runSynth(config, mod, tech, freq, maxopt, usesram) else: defaultfreq = 500 if tech == 'sky90' else 1500 From 45b82cd5c2c65206c18f3910a5277e80c4eae32d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 27 Apr 2024 17:12:58 -0700 Subject: [PATCH 5/6] Removed no-timing from lint-wally because there are no longer delay statements in the code --- bin/lint-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/lint-wally b/bin/lint-wally index d1fdc7dcc..cc658edc6 100755 --- a/bin/lint-wally +++ b/bin/lint-wally @@ -26,7 +26,7 @@ fi for config in ${configs[@]}; do # echo "$config linting..." - if !($verilator --no-timing --lint-only --quiet --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --lint-only --quiet --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" fails=$((fails+1)) From 055cfcb7173c08a9177f672c72cc35be610fbba9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 27 Apr 2024 19:51:23 -0700 Subject: [PATCH 6/6] Adjusted site setup based on new QUESTA_HOME --- site-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/site-setup.sh b/site-setup.sh index 4af031e35..acda541aa 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -17,7 +17,7 @@ export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change thi # Tools # Questa and Synopsys -export PATH=$QUESTA_HOME/questasim/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH +export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH # GCC export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib