From 000d713cb514705221db5b1bbbb7bb36634d1ab5 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 12 Jan 2022 14:22:18 -0600
Subject: [PATCH] Better solution to the integer divider interrupt interaction.

---
 pipelined/src/muldiv/intdivrestoring.sv   | 3 ++-
 pipelined/src/muldiv/muldiv.sv            | 4 ++--
 pipelined/src/privileged/trap.sv          | 2 +-
 pipelined/src/wally/wallypipelinedhart.sv | 2 +-
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/muldiv/intdivrestoring.sv b/pipelined/src/muldiv/intdivrestoring.sv
index f1c7c992f..e7155e4ec 100644
--- a/pipelined/src/muldiv/intdivrestoring.sv
+++ b/pipelined/src/muldiv/intdivrestoring.sv
@@ -36,6 +36,7 @@ module intdivrestoring (
   input  logic clk,
   input  logic reset,
   input  logic StallM,
+  input  logic TrapM,
   input  logic DivSignedE, W64E,
   input  logic DivE,
   //input logic [`XLEN-1:0] 	SrcAE, SrcBE,
@@ -116,7 +117,7 @@ module intdivrestoring (
   //////////////////////////////
 
  always_ff @(posedge clk) 
-    if (reset) begin
+    if (reset | TrapM) begin
         state <= IDLE; 
     end else if (DivStartE) begin 
         step <= 1;
diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv
index d7d063c4c..53eef5eb7 100644
--- a/pipelined/src/muldiv/muldiv.sv
+++ b/pipelined/src/muldiv/muldiv.sv
@@ -43,7 +43,7 @@ module muldiv (
 	       output logic 		DivBusyE, 
            output logic         DivE,
 	       // hazards
-	       input logic 		StallM, StallW, FlushM, FlushW 
+	       input logic 		StallM, StallW, FlushM, FlushW, TrapM 
 	       );
 
 	logic [`XLEN-1:0] MDUResultM;
@@ -61,7 +61,7 @@ module muldiv (
 	// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
 	assign DivE = MDUE & Funct3E[2];
 	assign DivSignedE = ~Funct3E[0];
-	intdivrestoring div(.clk, .reset, .StallM, .DivSignedE, .W64E, .DivE, 
+	intdivrestoring div(.clk, .reset, .StallM, .TrapM, .DivSignedE, .W64E, .DivE, 
 	                    .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
 		
 	// Result multiplexer
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index e4ad519cb..8412ad28e 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -71,7 +71,7 @@ module trap (
   assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
   assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
   assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
-  assign InterruptM = PendingInterruptM & ~(CommittedM | DivE);  // *** RT. temporary hack to prevent integer division from having an interrupt during divide.
+  assign InterruptM = PendingInterruptM & ~(CommittedM);  // *** RT. temporary hack to prevent integer division from having an interrupt during divide.
   // ideally this should be disabled for all but the first cycle. However I'm not familar with the internals of the integer divider.  This should (could) be an issue for
   // floating point and integer multiply.
   //assign ExceptionM = TrapM;
diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv
index 48e1c1c30..f11f5384d 100644
--- a/pipelined/src/wally/wallypipelinedhart.sv
+++ b/pipelined/src/wally/wallypipelinedhart.sv
@@ -358,7 +358,7 @@ module wallypipelinedhart (
          .ForwardedSrcAE, .ForwardedSrcBE, 
          .Funct3E, .Funct3M, .MDUE, .W64E,
          .MDUResultW, .DivBusyE,  .DivE,
-         .StallM, .StallW, .FlushM, .FlushW 
+         .StallM, .StallW, .FlushM, .FlushW, .TrapM 
       ); 
    end else begin // no M instructions supported
       assign MDUResultW = 0;