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https://github.com/openhwgroup/cvw
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50 lines
2.1 KiB
Systemverilog
50 lines
2.1 KiB
Systemverilog
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///////////////////////////////////////////
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// or.sv
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//
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// Written: David_Harris@hmc.edu 13 July 2021
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// Modified:
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//
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// Purpose: Various flavors of multiplexers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off DECLFILENAME */
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/* verilator lint_off UNOPTFLAT */
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// perform an OR of all the rows in an array, producing one output for each column
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// equivalent to assign y = a.or
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module or_rows #(parameter ROWS = 8, COLS=2) (
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input var logic [COLS-1:0] a[ROWS-1:0],
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output logic [COLS-1:0] y);
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logic [COLS-1:0] mid[ROWS-1:0];
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genvar row, col;
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generate
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for (col = 0; col < COLS; col++) begin
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assign mid[1][col] = a[0][col] | a[1][col];
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for (row=2; row < ROWS; row++)
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assign mid[row][col] = mid[row-1][col] | a[row][col];
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assign y[col] = mid[ROWS-1][col];
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end
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endgenerate
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endmodule
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_on DECLFILENAME */
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