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cvw/bugs.txt

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Lee Moore found another bug using imperas. An ITLB miss concurrent with a d cache flush did not interlock. The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
2023-02-03 05:52:21 +00:00
1. [ ] AMO should always generate store faults never load faults. We are generating both.
Test commit. please merge.
2023-01-23 18:53:31 +00:00
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