cvw/examples/asm/ch5/ch5.debug

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2021-12-18 01:45:26 +00:00
ch5: file format elf64-littleriscv
Disassembly of section .text:
0000000000010078 <_start>:
10078: 00402083 lw ra,4(zero) # 4 <_start-0x10074>
1007c: 00102423 sw ra,8(zero) # 8 <_start-0x10070>
10080: 00108133 add sp,ra,ra
10084: 00208463 beq ra,sp,1008c <done>
0000000000010088 <loop>:
10088: 0000006f j 10088 <loop>
Disassembly of section .riscv.attributes:
0000000000000000 <.riscv.attributes>:
0: 3241 addiw tp,tp,-16
2: 0000 unimp
4: 7200 ld s0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <_start-0x10064>
c: 0028 addi a0,sp,8
e: 0000 unimp
10: 7205 lui tp,0xfffe1
12: 3676 fld fa2,376(sp)
14: 6934 ld a3,80(a0)
16: 7032 0x7032
18: 5f30 lw a2,120(a4)
1a: 326d addiw tp,tp,-5
1c: 3070 fld fa2,224(s0)
1e: 615f 7032 5f30 0x5f307032615f
24: 3266 fld ft4,120(sp)
26: 3070 fld fa2,224(s0)
28: 645f 7032 5f30 0x5f307032645f
2e: 30703263 0x30703263
...