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32 lines
1.1 KiB
Systemverilog
32 lines
1.1 KiB
Systemverilog
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//performs the fsgnj/fsgnjn/fsgnjx RISCV instructions
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module fpusgn (SgnOpCodeE, SgnResultE, SgnFlagsE, SgnOp1E, SgnOp2E);
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input [63:0] SgnOp1E, SgnOp2E;
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input [1:0] SgnOpCodeE;
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output [63:0] SgnResultE;
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output [4:0] SgnFlagsE;
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wire AonesExp;
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//op code designation:
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//
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//00 - fsgnj - directly copy over sign value of SgnOp2E
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//01 - fsgnjn - negate sign value of SgnOp2E
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//10 - fsgnjx - XOR sign values of SgnOp1E & SgnOp2E
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//
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assign SgnResultE[63] = SgnOpCodeE[1] ? (SgnOp1E[63] ^ SgnOp2E[63]) : (SgnOp2E[63] ^ SgnOpCodeE[0]);
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assign SgnResultE[62:0] = SgnOp1E[62:0];
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//If the exponent is all ones, then the value is either Inf or NaN,
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//both of which will produce a QNaN/SNaN value of some sort. This will
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//set the invalid flag high.
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assign AonesExp = SgnOp1E[62]&SgnOp1E[61]&SgnOp1E[60]&SgnOp1E[59]&SgnOp1E[58]&SgnOp1E[57]&SgnOp1E[56]&SgnOp1E[55]&SgnOp1E[54]&SgnOp1E[53]&SgnOp1E[52];
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//the only flag that can occur during this operation is invalid
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//due to changing sign on already existing NaN
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assign SgnFlagsE = {AonesExp & SgnResultE[63], 1'b0, 1'b0, 1'b0, 1'b0};
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endmodule
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