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https://github.com/openhwgroup/cvw
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53 lines
2.2 KiB
Systemverilog
53 lines
2.2 KiB
Systemverilog
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///////////////////////////////////////////
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// comparator.sv
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//
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// Written: David_Harris@hmc.edu 8 December 2021
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// Modified:
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//
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// Purpose: Branch comparison
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module comparator #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [2:0] flags);
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logic [WIDTH-1:0] bbar, diff;
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logic carry, zero, neg, overflow, lt, ltu;
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// NOTE: This can be replaced by some faster logic optimized
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// to just compute flags and not the difference.
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// subtraction
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assign bbar = ~b;
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assign {carry, diff} = a + bbar;
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// condition code flags based on add/subtract output
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assign zero = (diff == 0);
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assign neg = diff[WIDTH-1];
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// overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign fron the first
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assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
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assign lt = neg ^ overflow;
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assign ltu = ~carry;
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assign flags = {zero, lt, ltu};
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endmodule
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