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https://github.com/openhwgroup/cvw
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26 lines
702 B
Systemverilog
26 lines
702 B
Systemverilog
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typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t;
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covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins);
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option.per_instance = 1;
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option.comment = "Fence.I";
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cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) {
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option.comment = "Number of times instruction is executed";
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bins count[] = {1};
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}
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endgroup
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function void test_fencei_sample(int hart, int issue);
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test_ins_rv64i_t ins;
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case (traceDataQ[hart][issue][0].inst_name)
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"fenci" : begin
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ins = new(hart, issue, traceDataQ);
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test_fencei_cg.sample(ins);
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end
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endcase
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endfunction
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