2022-02-09 22:20:05 +00:00
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Synthesis for RISC-V Microprocessor System-on-Chip Design
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2022-01-30 23:34:56 +00:00
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This subdirectory contains synthesis scripts for use with Synopsys
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2022-02-09 22:20:05 +00:00
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(snps) Design Compiler (DC). Synthesis commands are found in
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scripts/synth.tcl.
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2022-01-30 23:34:56 +00:00
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2022-02-09 22:20:05 +00:00
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Example Usage
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make synth DESIGN=wallypipelinedcore FREQ=300
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2022-01-30 23:34:56 +00:00
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2022-02-10 00:47:20 +00:00
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environment variables
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DESIGN
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Design provides the name of the output log. Default is synth.
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FREQ
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Frequency in Mhz. Default is 500
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CONFIG
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The wally configuration file. Default is rv32e.
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Examples.
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rv32e
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rv64gc
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rv32gc
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TECH
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The target standard cell library. Default is 130.
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90: skywater 90nm tt 25C.
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130: skywater 130nm tt 25C.
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SAIFPOWER
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Controls if power analysis is driven by switching factor or RTL modelsim simulation.
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When enabled requires a saif file named power.saif.
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Default is 0.
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0: switching factor power analysis
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1: RTL simulation driven power analysis.
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2022-02-09 22:20:05 +00:00
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Libraries in .synopsys_dc.setup file
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set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
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2022-01-30 23:34:56 +00:00
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