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https://github.com/openhwgroup/cvw
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52 lines
2.1 KiB
Systemverilog
52 lines
2.1 KiB
Systemverilog
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///////////////////////////////////////////
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// muldiv.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: M extension multiply and divide
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module muldiv (
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input logic clk, reset,
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// Decode Stage interface
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input logic [31:0] InstrD,
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// Execute Stage interface
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input logic [`XLEN-1:0] SrcAE, SrcBE,
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input logic MulDivE, W64E,
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// Writeback stage
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output logic [`XLEN-1:0] MulDivResultW,
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// hazards
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input logic FlushM, FlushW // ***fewer?
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);
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logic [`XLEN*2-1:0] ProdE;
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logic [`XLEN-1:0] MulDivResultE, MulDivResultM;
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assign ProdE = SrcAE * SrcBE;
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assign MulDivResultE = ProdE[`XLEN-1:0];
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floprc #(`XLEN) MulDivResultMReg(clk, reset, FlushM, MulDivResultE, MulDivResultM);
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floprc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, MulDivResultM, MulDivResultW);
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endmodule
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