2022-01-10 16:26:18 +00:00
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# riscvsingle.do
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# David_Harris@hmc.edu 10 January 2021
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# compile, optimize, and start the simulation
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vlog riscvsingle.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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# Add waveforms and run the simulation
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add wave /testbench/clk
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add wave /testbench/reset
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add wave -divider "Main Datapath"
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add wave /testbench/dut/PC
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add wave /testbench/dut/Instr
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2022-01-17 16:57:32 +00:00
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add wave /testbench/dut/ieu/dp/SrcA
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add wave /testbench/dut/ieu/dp/SrcB
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add wave /testbench/dut/ieu/dp/Result
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2022-01-10 16:26:18 +00:00
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add wave -divider "Memory Bus"
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add wave /testbench/MemWrite
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2022-01-17 16:57:32 +00:00
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add wave /testbench/IEUAdr
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2022-01-10 16:26:18 +00:00
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add wave /testbench/WriteData
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2022-01-17 16:57:32 +00:00
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run 210
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2022-01-10 16:26:18 +00:00
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view wave
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