2022-02-09 22:20:05 +00:00
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Synthesis for RISC-V Microprocessor System-on-Chip Design
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2022-01-30 23:34:56 +00:00
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This subdirectory contains synthesis scripts for use with Synopsys
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2022-02-09 22:20:05 +00:00
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(snps) Design Compiler (DC). Synthesis commands are found in
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scripts/synth.tcl.
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2022-02-09 22:20:05 +00:00
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Example Usage
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make synth DESIGN=wallypipelinedcore FREQ=500
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2022-02-10 00:47:20 +00:00
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environment variables
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DESIGN
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Design provides the name of the output log. Default is synth.
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FREQ
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Frequency in MHz. Default is 500
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CONFIG
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The Wally configuration file. The default is rv32e.
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Examples: rv32e, rv64gc, rv32gc
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TECH
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The target standard cell library. The default is sky130.
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sky90: skywater 90nm TT 25C
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sky130: skywater 130nm TT 25C
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SAIFPOWER
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Controls if power analysis is driven by switching factor or
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RTL modelsim simulation. When enabled requires a saif file
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named power.saif. The default is 0.
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0: switching factor power analysis
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1: RTL simulation driven power analysis.
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2023-11-09 07:00:33 +00:00
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-----
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Extra Tool (PPA)
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To run ppa analysis that hones into target frequency, you can type:
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python3 ppa/ppaSynth.py from the synthDC directory. This runs a sweep
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across all modules listed at the bottom of the ppaSynth.py file.
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