cvw/.gitmodules

[submodule "addins/riscv-dv"]
	path = addins/riscv-dv
	url = https://github.com/google/riscv-dv
[submodule "addins/embench-iot"]
	path = addins/embench-iot
	url = https://github.com/embench/embench-iot
	branch = embench-1.0-branch
[submodule "addins/coremark"]
	path = addins/coremark
	url = https://github.com/eembc/coremark
[submodule "addins/FreeRTOS-Kernel"]
	path = addins/FreeRTOS-Kernel
	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
[submodule "addins/vivado-boards"]
	path = addins/vivado-boards
	url = https://github.com/Digilent/vivado-boards/
[submodule "addins/riscv-arch-test"]
	path = addins/riscv-arch-test
	url = https://github.com/riscv-non-isa/riscv-arch-test
	branch = dev
[submodule "addins/branch-predictor-simulator"]
	path = addins/branch-predictor-simulator
	url = https://github.com/ross144/branch-predictor-simulator
[submodule "addins/ahbsdc"]
	path = addins/ahbsdc
	url = https://github.com/JacobPease/ahbsdc.git
[submodule "addins/verilog-ethernet"]
	sparseCheckout = true
	path = addins/verilog-ethernet
	url = https://github.com/ross144/verilog-ethernet.git
[submodule "cvw-arch-verif"]
	path = addins/cvw-arch-verif
	url = https://github.com/openhwgroup/cvw-arch-verif
[submodule "addins/riscvISACOV"]
	path = addins/riscvISACOV
	url = https://github.com/riscv-verification/riscvISACOV.git
Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00			`[submodule "addins/riscv-dv"]`
			`path = addins/riscv-dv`
			`url = https://github.com/google/riscv-dv`
			`[submodule "addins/embench-iot"]`
			`path = addins/embench-iot`
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo 2022-06-13 23:33:10 +00:00			`url = https://github.com/embench/embench-iot`
changed the default branch of embench 2022-07-21 17:14:05 +00:00			`branch = embench-1.0-branch`
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00			`[submodule "addins/coremark"]`
			`path = addins/coremark`
			`url = https://github.com/eembc/coremark`
pulling in FreeRTOS/kernel Submodule 2023-06-13 17:41:18 +00:00			`[submodule "addins/FreeRTOS-Kernel"]`
			`path = addins/FreeRTOS-Kernel`
			`url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git`
Added new submodule for digilent fpga boards. 2023-07-17 21:25:37 +00:00			`[submodule "addins/vivado-boards"]`
			`path = addins/vivado-boards`
			`url = https://github.com/Digilent/vivado-boards/`
Added back riscv-arch-test fresh 2023-11-15 13:48:33 +00:00			`[submodule "addins/riscv-arch-test"]`
			`path = addins/riscv-arch-test`
			`url = https://github.com/riscv-non-isa/riscv-arch-test`
Update riscv-arch-test submodule 2024-06-19 06:34:02 +00:00			`branch = dev`
Swap in branch predictor simulator handling compressed instruction offsets 2023-11-22 00:42:41 +00:00			`[submodule "addins/branch-predictor-simulator"]`
			`path = addins/branch-predictor-simulator`
			`url = https://github.com/ross144/branch-predictor-simulator`
Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue 2023-12-11 20:12:38 +00:00			`[submodule "addins/ahbsdc"]`
			`path = addins/ahbsdc`
Clean up .gitmodules file to eliminate warnings when cloning 2024-06-30 18:34:57 +00:00			`url = https://github.com/JacobPease/ahbsdc.git`
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo. 2024-07-18 23:22:26 +00:00			`[submodule "addins/verilog-ethernet"]`
			`sparseCheckout = true`
			`path = addins/verilog-ethernet`
			`url = https://github.com/ross144/verilog-ethernet.git`
Adding RVVI Functional Coverage Support 2024-08-07 09:19:05 +00:00			`[submodule "cvw-arch-verif"]`
Fix creating cvw-arch-verif work directory 2024-08-08 12:25:28 +00:00			`path = addins/cvw-arch-verif`
Adding RVVI Functional Coverage Support 2024-08-07 09:19:05 +00:00			`url = https://github.com/openhwgroup/cvw-arch-verif`
Fixed a subtle questa sim bug with imperasDV. On some linux systems vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV libraries are 64-bit. vsim must run in 64-bit mode. 2024-08-29 21:00:52 +00:00			`[submodule "addins/riscvISACOV"]`
			`path = addins/riscvISACOV`
Updated riscvISACOV submodule to https instead of ssh. 2024-08-29 21:54:47 +00:00			`url = https://github.com/riscv-verification/riscvISACOV.git`