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12 lines
183 B
Systemverilog
12 lines
183 B
Systemverilog
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module BUFGCE (input logic I, input logic CE, output logic O);
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logic CE_Q;
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always_latch begin
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if(~I) begin
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CE_Q <= CE;
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end
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end
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assign O = CE_Q & I;
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endmodule
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