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///////////////////////////////////////////
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// pmachecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and identifies attributes of
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// the memory region accessed.
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// Can report illegal accesses to the trap unit and cause a fault.
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//
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// A component of the Wally configurable RISC-V project.
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//
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2023-01-10 19:35:20 +00:00
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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2023-01-10 19:35:20 +00:00
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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2023-01-10 19:35:20 +00:00
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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2021-04-22 19:34:02 +00:00
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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2022-01-07 12:58:40 +00:00
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////////////////////////////////////////////////////////////////////////////////////////////////
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2021-04-22 19:34:02 +00:00
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`include "wally-config.vh"
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module pmachecker (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] Size,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
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output logic Cacheable, Idempotent, SelTIM,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAmoAccessFaultM
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);
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logic PMAAccessFault;
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logic AccessRW, AccessRWX, AccessRX;
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logic [10:0] SelRegions;
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logic AtomicAllowed;
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// Determine what type of access is being made
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assign AccessRW = ReadAccessM | WriteAccessM;
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assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
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assign AccessRX = ReadAccessM | ExecuteAccessF;
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// Determine which region of physical memory (if any) is being accessed
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adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
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2022-08-27 03:45:43 +00:00
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// Only non-core RAM/ROM memory regions are cacheable
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assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];
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assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
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assign AtomicAllowed = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
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assign SelTIM = SelRegions[10] | SelRegions[9];
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// Detect access faults
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assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;
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assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
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assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault;
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endmodule
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2021-07-02 18:56:49 +00:00
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