mirror of
https://github.com/openhwgroup/cvw
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116 lines
4.9 KiB
Markdown
116 lines
4.9 KiB
Markdown
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These are the testvectors (TV) to test the floating-point units using
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Berkeley TestFloat written originally by John Hauser. TestFloat
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requires both TestFloat and SoftFloat.
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The locations at time of this README is found here:
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TestFloat-3e: http://www.jhauser.us/arithmetic/TestFloat.html
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SoftFloat-3e: http://www.jhauser.us/arithmetic/SoftFloat.html
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These files have been compiled on a x86_64 environment by going into
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the build/Linux-x86_64-GCC directory and typing make. A script
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createX.sh (e.g., create_vectors32.sh) has been included that create
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the TV for each rounding mode and operation. These scripts must be
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run in the build directory of TestFloat.
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After each TV has been created a script (included) is run called
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undy.sh that puts an underscore between vector to allow SystemVerilog
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readmemh to read correctly.
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./undy.sh file.tv
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To remove all the underscores from all the TV files, one can run the
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command that will add underscores appropriately to all the files.
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sed -i 's/ /_/g' *.tv
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Note: due to size, the fxx_fma_xx.tv vectors are not included.
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However, they can easily be created with the create scripts.
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James Stine
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10/7/2021
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File Sizes
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600 1800 17400 f32_f64_rd.tv
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600 1800 17400 f32_f64_rne.tv
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600 1800 17400 f32_f64_ru.tv
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600 1800 17400 f32_f64_rz.tv
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600 1800 17400 f32_i64_rd.tv
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600 1800 17400 f32_i64_rne.tv
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600 1800 17400 f32_i64_ru.tv
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600 1800 17400 f32_i64_rz.tv
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600 1800 17400 f32_ui64_rd.tv
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600 1800 17400 f32_ui64_rne.tv
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600 1800 17400 f32_ui64_ru.tv
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600 1800 17400 f32_ui64_rz.tv
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46464 185856 2509056 f64_add_rd.tv
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46464 185856 2509056 f64_add_rne.tv
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46464 185856 2509056 f64_add_ru.tv
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46464 185856 2509056 f64_add_rz.tv
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46464 185856 2509056 f64_div_rd.tv
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46464 185856 2509056 f64_div_rne.tv
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46464 185856 2509056 f64_div_ru.tv
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46464 185856 2509056 f64_div_rz.tv
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768 2304 22272 f64_f32_rd.tv
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768 2304 22272 f64_f32_rne.tv
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768 2304 22272 f64_f32_ru.tv
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768 2304 22272 f64_f32_rz.tv
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6133248 30666240 435460608 f64_fma_rd.tv
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6133248 30666240 435460608 f64_fma_rne.tv
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6133248 30666240 435460608 f64_fma_ru.tv
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6133248 30666240 435460608 f64_fma_rz.tv
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768 2304 22272 f64_i32_rd.tv
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768 2304 22272 f64_i32_rne.tv
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768 2304 22272 f64_i32_ru.tv
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768 2304 22272 f64_i32_rz.tv
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46464 185856 2509056 f64_mul_rd.tv
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46464 185856 2509056 f64_mul_rne.tv
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46464 185856 2509056 f64_mul_ru.tv
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46464 185856 2509056 f64_mul_rz.tv
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768 2304 28416 f64_sqrt_rd.tv
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768 2304 28416 f64_sqrt_rne.tv
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768 2304 28416 f64_sqrt_ru.tv
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768 2304 28416 f64_sqrt_rz.tv
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46464 185856 2509056 f64_sub_rd.tv
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46464 185856 2509056 f64_sub_rne.tv
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46464 185856 2509056 f64_sub_ru.tv
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46464 185856 2509056 f64_sub_rz.tv
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768 2304 22272 f64_ui32_rd.tv
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768 2304 22272 f64_ui32_rne.tv
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768 2304 22272 f64_ui32_ru.tv
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768 2304 22272 f64_ui32_rz.tv
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372 1116 7812 i32_f32_rd.tv
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372 1116 7812 i32_f32_rne.tv
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372 1116 7812 i32_f32_ru.tv
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372 1116 7812 i32_f32_rz.tv
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372 1116 10788 i32_f64_rd.tv
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372 1116 10788 i32_f64_rne.tv
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372 1116 10788 i32_f64_ru.tv
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372 1116 10788 i32_f64_rz.tv
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756 2268 21924 i64_f32_rd.tv
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756 2268 21924 i64_f32_rne.tv
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756 2268 21924 i64_f32_ru.tv
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756 2268 21924 i64_f32_rz.tv
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756 2268 27972 i64_f64_rd.tv
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756 2268 27972 i64_f64_rne.tv
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756 2268 27972 i64_f64_ru.tv
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756 2268 27972 i64_f64_rz.tv
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372 1116 7812 ui32_f32_rd.tv
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372 1116 7812 ui32_f32_rne.tv
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372 1116 7812 ui32_f32_ru.tv
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372 1116 7812 ui32_f32_rz.tv
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372 1116 10788 ui32_f64_rd.tv
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372 1116 10788 ui32_f64_rne.tv
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372 1116 10788 ui32_f64_ru.tv
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372 1116 10788 ui32_f64_rz.tv
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756 2268 21924 ui64_f32_rd.tv
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756 2268 21924 ui64_f32_rne.tv
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756 2268 21924 ui64_f32_ru.tv
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756 2268 21924 ui64_f32_rz.tv
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756 2268 27972 ui64_f64_rd.tv
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756 2268 27972 ui64_f64_rne.tv
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756 2268 27972 ui64_f64_ru.tv
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756 2268 27972 ui64_f64_rz.tv
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25313952 125751264 1783125024 total
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