cvw/fpga/constraints/marked_debug.txt

wally/wallypipelinedcore.sv: logic             PCM
wally/wallypipelinedcore.sv: logic    TrapM
wally/wallypipelinedcore.sv: logic                InstrValidM
wally/wallypipelinedcore.sv: logic                 InstrM
lsu/lsu.sv: logic        IEUAdrM
lsu/lsu.sv: logic        PAdrM
lsu/lsu.sv: logic        ReadDataM
lsu/lsu.sv: logic        WriteDataM
lsu/lsu.sv: logic       MemRWM
mmu/hptw.sv: logic	   SATP_REGW
privileged/csr.sv: logic       MENVCFG_REGW
privileged/csr.sv: logic       SENVCFG_REGW
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory. 2023-01-21 01:43:18 +00:00			`wally/wallypipelinedcore.sv: logic PCM`
Added menvcfg to debugger for checking what linux has configured. 2023-11-19 19:44:22 +00:00			`wally/wallypipelinedcore.sv: logic TrapM`
Removed mark_debug vivado directive from source code. Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger. Files output to temporary directory. 2023-01-21 01:43:18 +00:00			`wally/wallypipelinedcore.sv: logic InstrValidM`
Added menvcfg to debugger for checking what linux has configured. 2023-11-19 19:44:22 +00:00			`wally/wallypipelinedcore.sv: logic InstrM`
			`lsu/lsu.sv: logic IEUAdrM`
			`lsu/lsu.sv: logic PAdrM`
			`lsu/lsu.sv: logic ReadDataM`
			`lsu/lsu.sv: logic WriteDataM`
			`lsu/lsu.sv: logic MemRWM`
			`mmu/hptw.sv: logic SATP_REGW`
			`privileged/csr.sv: logic MENVCFG_REGW`
			`privileged/csr.sv: logic SENVCFG_REGW`