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https://github.com/openhwgroup/cvw
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59 lines
2.0 KiB
Systemverilog
59 lines
2.0 KiB
Systemverilog
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///////////////////////////////////////////
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// zbb.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
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// Created: 2 February 2023
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// Modified:
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//
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// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions)
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] Funct3, // Indicates operation to perform
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input logic [6:0] Funct7, // Indicates operation to perform
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output logic [WIDTH-1:0] ZBBResult); // ZBC result
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logic [WIDTH-1:0] OrcBResult;
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logic [WIDTH-1:0] Rev8Result;
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genvar i;
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for (i=0;i<WIDTH;i+=8) begin:loop
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assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
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assign Rev8Result[WIDTH-i:WIDTH-i-7] = A[i+7:i];
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end
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//can replace with structural mux by looking at bit 4 in rs2 field
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always_comb begin
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case ({Funct7, Funct3, B})
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15'b0010100_101_00111: ZBBResult = OrcBResult;
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15'b0110100_101_11000: ZBBResult = Rev8Result;
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15'b0110101_101_11000: ZBBResult = Rev8Result;
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endcase
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end
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endmodule
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