cvw/pipelined/testbench/common/logging.sv

module logging(
  input logic clk, reset,
  input logic [31:0] HADDR,
  input logic [1:0]  HTRANS);

  always @(posedge clk)
    if (HTRANS != 2'b00 & HADDR == 0)
      $display("%t Warning: access to memory address 0\n", $realtime);
endmodule
Moved the test bench modules to a common directory. 2021-07-30 19:16:14 +00:00			`module logging(`
			`input logic clk, reset,`
			`input logic [31:0] HADDR,`
			`input logic [1:0] HTRANS);`

			`always @(posedge clk)`
Replaced && and \|\| with & and \| in non-fp files per new style guidelines 2022-01-02 21:47:21 +00:00			`if (HTRANS != 2'b00 & HADDR == 0)`
Moved the test bench modules to a common directory. 2021-07-30 19:16:14 +00:00			`$display("%t Warning: access to memory address 0\n", $realtime);`
			`endmodule`