mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
34 lines
1.3 KiB
Plaintext
34 lines
1.3 KiB
Plaintext
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wally/wallypipelinedcore.sv: logic PCM
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wally/wallypipelinedcore.sv: logic TrapM
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wally/wallypipelinedcore.sv: logic InstrValidM
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wally/wallypipelinedcore.sv: logic InstrM
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lsu/lsu.sv: logic IEUAdrM
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lsu/lsu.sv: logic MemRWM
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mmu/hptw.sv: logic SATP_REGW
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uncore/uartPC16550D.sv : logic MCR
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uncore/uartPC16550D.sv : logic FCR
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uncore/uartPC16550D.sv : logic MSR
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uncore/uartPC16550D.sv : logic DTRb
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uncore/uartPC16550D.sv : logic INTR
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uncore/uartPC16550D.sv : logic RXRDYb
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uncore/uartPC16550D.sv : logic TXRDYb
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uncore/uartPC16550D.sv : logic RXerrIP
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uncore/uartPC16550D.sv : logic IER
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uncore/uartPC16550D.sv : logic LSR
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uncore/uartPC16550D.sv : logic SCR
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uncore/uartPC16550D.sv : statetype txstate
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uncore/uartPC16550D.sv : logic RBR
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uncore/uartPC16550D.sv : logic rxparityerr
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uncore/uartPC16550D.sv : logic LCR
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uncore/uartPC16550D.sv : logic intrID
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uncore/uartPC16550D.sv : logic rxdataavailintr
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uncore/uartPC16550D.sv : logic fifoenabled
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uncore/uartPC16550D.sv : logic rxfifoentries
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uncore/uartPC16550D.sv : logic txsrfull
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uncore/uartPC16550D.sv : logic txhrfull
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uncore/uartPC16550D.sv : logic txfifofull
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uncore/uartPC16550D.sv : logic txfifotail
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uncore/uartPC16550D.sv : logic txfifohead
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uncore/uartPC16550D.sv : logic rxfifotriggered
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uncore/uartPC16550D.sv : logic rxdataready
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